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69030
69030 Dual HiQVideo Accelerator with 4MB Embedded Memory Databook Revision 1.3
November 1999
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Copyright Notice
Copyright 1999 Intel Corporation Chips and Technologies, Inc. has been integrated into the Platform Components Group (PCG) of Intel Corporation. ALL RIGHTS RESERVED. This manual is copyrighted by Intel Corporation. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, in any form or by any means - electronic, mechanical, magnetic, optical, chemical, manual, or otherwise - any part of this publication without the express written permission of Intel Corporation.
Restricted Rights Legend
Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at 252.277-7013.
Trademark Acknowledgment
CHIPS Logo is a registered trademark of Intel Corporation. HiQVideo, HiQV32, HiQV64, Unified Architecture, Unified Memory, and XRAM Video Cache are trademarks of Intel Corporation (formerly Chips and Technologies, Inc.) MS-DOS, Windows, Win98, Win95, WinNT4 and WinNT5 are trademarks of Microsoft Corporation. All other trademarks and brands are the property of their respective owners.
Disclaimer
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 69030 graphics accelerator may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel Corporation www.intel.com or call 1-800-548-4725
efmp69030 Databook
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69030 Dual HiQVideoAccelerator with 4MB Embedded Memory
Embedded SDRAM memory * 4 MB embedded memory * 83 MHz SDRAM operation Dual Independent Display * Different or same display image CRT/TV and Flat Panel * Independent display timing and resolution for CRT/TV and Flat Panel Single View Display Mode * up to 1600x1200 64K color @ 60 Hz Dual Independent Display Mode * up to 1280x1024 256 color @ 60 Hz HiQColorTM Technology implements TMED (Temporal Modulated Energy Distribution) on STN displays: * 16.7 Million colors * Crisper display * 256 gray shades * Reduced motion artifacts Graphics Acceleration * 64-bit Single Cycle BitBLT Engine * System/Screen-to-Screen BitBLTs * 256 3-Op Raster-Operations * Color Expansion * Instant Full Screen Page Flip * Transparent, Source, Destination BitBLT NTSC / PAL TV-Out Support * Advanced Flicker Reduction Filter Circuitry * Underscan Compensation Simultaneous Hardware Cursor and Pop-up Window Support * 2 hardware cursors and 1 pop-up icon * 64x64 pixels by 4 colors * 128x128 pixels by 2 colors External LVDS and PanelLinkTM Support for TFT and DSTN Panels Low Power Consumption Microsoft PC 98 and PC 99 Compliant Accelerated Driver Support * Windows 3.1, Windows 95, Windows 98, NT 4.0 and NT 5.0, etc. * CD-I, Video CD, Open MPEG Dual Multimedia Accelerator Engines * Color Space Conversion (YUV 422-RGB) * Horizontal and Vertical Interpolation * Double buffering support for YUV and 15/16 RGB * Color Key Video Overlay Industry-Standard Host Bus Interface Support * Frame AGP * PCI Flexible Panel Support * TFT, DSTN, SSTN, EL, Plasma * Color and Monochrome * Resolution Support for: * VGA, SVGA, XGA, SXGA, UXGA * Quarter VGA 320x240, 320x200 * 16:9 Aspect Ratio Panels: 1024x600 * Auto Panel Power On/Off Sequencing Multimedia Capture Features * Zoom Video Port * Hardware interrupt support for VPE (Microsoft(R), Video Port Extension) * YUV/RGB data capture from video port or host bus * Interlaced/Frame/Bob Video Capture Integrated Clock Synthesizers * 170 MHz RAMDAC * 83 MHz Memory Clock with PLL Advance On-Chip Power Management * Standby Mode * 0 V Suspend * Panel-Off Power-Saving Mode * 4 GPIO Pins * Activity Detection Output Pin Standards Supported * Fully IBM(R) VGA Compatible * VESA DPMS and DDC 1/2 * Advanced Power Management * ACPI Compliant Other Features * 3.3 V Operation * 272-ball PBGA package * 256-ball mini-BGA package
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69030 Software Support Features
Drivers Features * Dual Independent Displays * High Performance Accelerated drivers * Compatible across HiQVideo family * Auto Panning Support * LCD/CRT/Simultaneous Mode Support * Auto Resolution Change * HW Stretching/Scaling * Double Buffering * Internationalization * Direct Draw 6.0 support * Dynamic Resolution Switching * VESA DDC extensions * VESA DPMS extensions * Property Sheet to change Refresh/ Display * Seamless Windows Support * Boot time resolution adjustment * DIVE, EnDIVE * DCAF Multimedia Software * Video Port Manager for ZV Port * PCVideo DLL plus Tuner with DK Board * VPE Software Utilities * DebugVGA * Auto testing of all video modes * ChipsVGA * ChipsEXT Software Documentation * BIOS OEM Reference Guide * Display Driver User's Guide * Utilities User's Guide * Release Notes for BIOS, Drivers, and Utilities BIOS Features * Customized mode support for nonstandard resolution panels * VGA Compatible BIOS * PnP Support * VESA VBE 2.0 (incl. DPMS) * DDC 1, DDC 2AB * Text and Graphics Expansion * Auto Centering * 44 (40) K BIOS * CRT, LCD, Simultaneous display modes * Auto Resolution Switch * Multiple Refresh Rates * NTSC/PAL support * Extended Modes * Extended BIOS Functions * 1024x768 TFT, DSTN Color Panels * Multiple Panel Support (8 panels builtin) * Get Panel Type Function * H/W Cursor / Pop-up Interface * Monitor Detect * SMI and Hot Key support System BIOS Hooks * Set Active Display Type * Save/Restore Video State * Setup Memory for Save/Restore * SMI Entry Point * Int 15 Calls after POST, Set Mode BIOS Modify Program (BMP) * Clocks * Mode support * Panel Tables * Int 15 Hooks * Monitor Sensing Driver Support * * Windows 95, Windows 98 * Windows NT 4.0, NT 5.0 * Portrait Driver Support * For others, Contact Intel Corporation
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Revision History
Revision 0.5 0.6 1.0 1.1 1.2 Date 8/14/98 10/1/98 03/22/99 07/16/99 11/15/99 By BB/bjb BB/bjb BB/dam AP/dak MK/dak Comments First Draft - Official Release Under NDA. Removed appendices - update Chapter 2. Incorporated Engineering and Technical Editing Changes. Updated Chapters 2, 7, 8, 9, 14, 15, 16, 18, Appendix B MCLK change to 83MHz Minor edits to Chapter 1, Appendix B GPI04 and GPI07 removed. Changed AC Test Conditions in Chapter 3, table 3-6 Remove NDA and Confidental stamps Added mBGA package pinout and pin numbering Added mBGA package mechanical specifications
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Chapter 1 Introduction / Overview
High Performance Embedded Memory ....................................................................................... 1-1 Dual Independent Display ........................................................................................................... 1-1 Dual-Pipe Simultaneous Mode .................................................................................................... 1-1 Dual-Pipe Mosaic Mode .............................................................................................................. 1-2 Single-Pipe Mode ........................................................................................................................ 1-2 Dual Video Accelerator Engines .................................................................................................. 1-3 HiQColorTM Technology ............................................................................................................. 1-3 Acceleration for All Panels and All Modes .................................................................................. 1-3 Television NTSC/PAL Flicker Free Output and Underscan ........................................................ 1-3 HiQVideoTM Capture/Playback Support ..................................................................................... 1-3 Versatile Panel Support ............................................................................................................... 1-4 Integrated RAMDAC and Clock Synthesizer ............................................................................... 1-4 Low Power Consumption ............................................................................................................ 1-4 Software Compatibility / Flexibility ............................................................................................... 1-4
Chapter 2 Pin Descriptions
Introduction .................................................................................................................................. 2-1 B69030 Pin Diagram, Top View .................................................................................................. 2-1 B69030 Pin Diagram, Bottom View ............................................................................................. 2-2 M69030 Pin Diagram, Top View .................................................................................................. 2-3 M69030 Pin Diagram, Bottom View ............................................................................................ 2-4 B69030 and M69030 PCI/AGP Bus Interface ............................................................................. 2-5 B69030 and M69030 Configuration Pins and ROM Interface ..................................................... 2-8 B69030 and M69030 Flat Panel Display Interface ...................................................................... 2-9 B69030 and M69030 CRT Interface .......................................................................................... 2-12 B69030 and M69030 Video Interface ........................................................................................ 2-13 B69030 and M69030 Miscellaneous Pins ................................................................................. 2-14 B69030 and M69030 Power and Ground Pins .......................................................................... 2-15 B69030 and M69030 Reserved and No Connection Pins ......................................................... 2-17
Chapter 3 Electrical Specifications
Introduction .................................................................................................................................. 3-1
Chapter 4 Mechanical Specifications
Introduction .................................................................................................................................. 4-1
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Chapter 5 I/O and Memory Address Maps
Introduction .................................................................................................................................. 5-1 VGA-Compatible Address Map ................................................................................................... 5-1 Address Maps for Going Beyond VGA ........................................................................................ 5-2 Lower Memory Map ..................................................................................................................... 5-2 I/O and Sub-Addressed Register Map ........................................................................................ 5-2 Sub-Indexing Indices and Data Ports .......................................................................................... 5-4 Register Shadowing Schemes for Dual-Pipe .............................................................................. 5-5 I/O Space Register Shadowing ................................................................................................... 5-5 Memory Space Register Shadowing ........................................................................................... 5-7 Video Playback Engine Register Cross-Sharing ......................................................................... 5-7 Two-Way Sub-Indexed Register Indices ..................................................................................... 5-9 Upper Memory Map -- Dual-Pipe Mapping ................................................................................ 5-10 Upper Memory Map -- Multiple-Endian Mapping ....................................................................... 5-10
Chapter 6 Register Summaries
Introduction .................................................................................................................................. 6-1
Chapter 7 PCI Configuration Registers
Introduction .................................................................................................................................. 7-1 VENDIDD Vendor ID Register ......................................................................................... 7-2 DEVID Device ID Register ......................................................................................... 7-2 DEVCTL Device Control Register ................................................................................. 7-3 DEVSTAT Device Status Register ................................................................................... 7-5 REV Revision ID Register ...................................................................................... 7-7 PRG Register-Level Programming Interface Register ............................................ 7-7 SUB Sub-Class Code Register ............................................................................... 7-8 BASE Base Class Code Register ............................................................................. 7-8 HDR Header Type Register .................................................................................... 7-9 MBASE Memory Base Address Register .................................................................. 7-10 SUBVENDID Subsystem Vendor ID Register .................................................................... 7-11 SUBDEVDID Subsystem Device ID Register .................................................................... 7-11 INTLINE Interrupt Line Register .................................................................................. 7-12 INTPIN Interrupt Pin Register ................................................................................... 7-12 RBASE ROM Base Address Register ....................................................................... 7-13 SUBVENDSET Subsystem Vendor ID Set Register ............................................................. 7-14 SUBDEVSET Subsystem Device ID Set ............................................................................ 7-14
Chapter 8 General Control and Status Registers
Introduction .................................................................................................................................. 8-1 ST00 Input Status Register 0 ................................................................................... 8-2 ST01 Input Status Register 1 ................................................................................... 8-3 FCR Feature Control Register ................................................................................ 8-4 MSR Miscellaneous Output Register ...................................................................... 8-5 IOSS I/O Space Shadowing Register ...................................................................... 8-7 MSS Memory Space Shadowing Register ............................................................ 8-13
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Chapter 9 CRT Controller Registers
Introduction .................................................................................................................................. 9-1 CRX CRT Controller Index Register ....................................................................... 9-2 CR00 Horizontal Total Register ................................................................................ 9-3 CR01 Horizontal Display Enable End Register ........................................................ 9-3 CR02 Horizontal Blanking Start Register ................................................................. 9-4 CR03 Horizontal Blanking End Register .................................................................. 9-5 CR04 Horizontal Sync Start Register ....................................................................... 9-6 CR05 Horizontal Sync End Register ........................................................................ 9-7 CR06 Vertical Total Register .................................................................................... 9-8 CR07 Overflow Register ........................................................................................... 9-9 CR08 Preset Row Scan Register ........................................................................... 9-13 CR09 Maximum Scanline Register ........................................................................ 9-14 CR0A Text Cursor Start Register ........................................................................... 9-16 CR0B Text Cursor End Register ............................................................................. 9-17 CR0C Start Address High Register ......................................................................... 9-18 CR0D Start Address Low Register ......................................................................... 9-19 CR0E Text Cursor Location High Register ............................................................. 9-20 CR0F Text Cursor Location Low Register .............................................................. 9-20 CR10 Vertical Sync Start Register ......................................................................... 9-21 CR11 Vertical Sync End Register .......................................................................... 9-22 CR12 Vertical Display Enable End Register .......................................................... 9-23 CR13 Offset Register ............................................................................................. 9-23 CR14 Underline Location Register ......................................................................... 9-24 CR15 Vertical Blanking Start Register ................................................................... 9-26 CR16 Vertical Blanking End Register .....................................................................9-26 CR17 CRT Mode Control ....................................................................................... 9-27 CR18 Line Compare Register ................................................................................ 9-30 CR22 Memory Read Latch Data Register .............................................................. 9-30 CR30 Extended Vertical Total Register .................................................................. 9-31 CR31 Extended Vertical Display End Register ...................................................... 9-32 CR32 Extended Vertical Sync Start Register ......................................................... 9-33 CR33 Extended Vertical Blanking Start Register ................................................... 9-34 CR38 Extended Horizontal Total Register ............................................................. 9-35 CR3C Extended Horizontal Blanking End Register ................................................ 9-36 CR40 Extended Start Address Register ................................................................. 9-37 CR41 Extended Span Register .............................................................................. 9-38 CR70 Interlace Control Register ............................................................................9-38 CR71 NTSC/PAL Video Output Control Register ................................................... 9-39 CR72 NTSC/PAL Horizontal Serration 1 Start Register ......................................... 9-40 CR73 NTSC/PAL Horizontal Serration 2 Start Register ......................................... 9-40 CR74 NTSC/PAL Horizontal Pulse Width Register ................................................ 9-41 CR75 NTSC/PAL Filtering Burst Read Length Register ........................................ 9-42 CR76 NTSC/PAL Filtering Burst Read Quantity Register ...................................... 9-42 CR77 NTSC/PAL Filtering Control Register ........................................................... 9-43 CR78 NTSC/PAL Vertical Reduction Register ....................................................... 9-44 CR79 NTSC/PAL Horizontal Total Fine Adjust Register ........................................ 9-45
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Chapter 10 Sequencer Registers
Introduction ................................................................................................................................ 10-1 SRX Sequencer Index Register ............................................................................ 10-2 SR00 Reset Register ............................................................................................. 10-2 SR01 Clocking Mode Register ............................................................................... 10-3 SR02 Plane Mask Register .................................................................................... 10-4 SR03 Character Map Select Register .................................................................... 10-5 SR04 Memory Mode Register ................................................................................ 10-7 SR07 Horizontal Character Counter Reset Register .............................................. 10-8
Chapter 11 Graphics Controller Registers
Introduction ................................................................................................................................ 11-1 GRX Graphics Controller Index Register .............................................................. 11-2 GR00 Set/Reset Register ....................................................................................... 11-2 GR01 Enable Set/Reset Register ........................................................................... 11-3 GR02 Color Compare Register .............................................................................. 11-3 GR03 Data Rotate Register .................................................................................... 11-4 GR04 Read Plane Select Register ......................................................................... 11-5 GR05 Graphics Mode Register .............................................................................. 11-6 GR06 Miscellaneous Register ................................................................................ 11-9 GR07 Color Don't Care Register .......................................................................... 11-10 GR08 Bit Mask Register ....................................................................................... 11-10
Chapter 12 Attribute Controller Registers
Introduction ................................................................................................................................ 12-1 ARX Attribute Controller Index Register ............................................................... 12-2 AR00-AR0F Palette Registers 0-F ................................................................................... 12-2 AR10 Mode Control Register ................................................................................. 12-3 AR11 Overscan Color Register .............................................................................. 12-5 AR12 Memory Plane Enable Register ................................................................... 12-6 AR13 Horizontal Pixel Panning Register ................................................................ 12-7 AR14 Color Select Register ................................................................................... 12-8
Chapter 13 Palette Registers
Introduction ................................................................................................................................ 13-1 PALMASK Palette Data Mask Register ......................................................................... 13-3 PALSTATE Palette State Register .................................................................................. 13-3 PALRX Palette Read Index Register ........................................................................ 13-4 PALWX Palette Write Index Register ........................................................................ 13-4 PALDATA Palette Data Register ................................................................................... 13-5
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Chapter 14 Extension Registers
Introduction ................................................................................................................................ 14-1 XRX Extension Register Index Register ...............................................................14-3 XR00 Vendor ID Low Register ............................................................................... 14-3 XR01 Vendor ID High Register .............................................................................. 14-4 XR02 Device ID Low Register ................................................................................ 14-4 XR03 Device ID High Register ............................................................................... 14-5 XR04 Revision ID Register .................................................................................... 14-5 XR05 Linear Base Address Low Register .............................................................. 14-6 XR06 Linear Base Address High Register ............................................................. 14-6 XR08 Host Bus Configuration Register .................................................................. 14-7 XR09 I/O Control Register ..................................................................................... 14-8 XR0A Frame Buffer Mapping Register ................................................................... 14-9 XR0B PCI Burst Write Support Register .............................................................. 14-11 XR0E Frame Buffer Page Select Register ........................................................... 14-12 XR20 BitBLT Configuration Register .................................................................... 14-13 XR40 Memory Access Control Register ............................................................... 14-14 XR41-XR4F Memory Configuration Registers ................................................................ 14-14 XR60 Video Pin Control Register ......................................................................... 14-15 XR61 DPMS Sync Control Register ..................................................................... 14-16 XR62 GPIO Pin Control Register ......................................................................... 14-17 XR63 GPIO Pin Data Register ............................................................................. 14-18 XR67 Pin Tri-State Control Register .................................................................... 14-19 XR70 Configuration Pins 0 Register .................................................................... 14-20 XR71 Configuration Pins 1 Register .................................................................... 14-22 XR80 Pixel Pipeline Configuration 0 Register ...................................................... 14-23 XR81 Pixel Pipeline Configuration 1 Register ...................................................... 14-25 XR82 Pixel Pipeline Configuration 2 Register ...................................................... 14-26 XR88 Alternate Font Location Control ................................................................. 14-27 XR8A Alternate Font Location Start Offset Low ................................................... 14-28 XR8B Alternate Font Location Start Offset High .................................................. 14-28 XR8C Alternate Font Location Counter Trigger Count ......................................... 14-29 XR8E Alternate Font Location Copy Read Burst Limit ......................................... 14-29 XR90-XR95 Software Flag Registers ............................................................................. 14-30 XRA0 Cursor 1 Control Register ..........................................................................14-31 XRA1 Cursor 1 Vertical Extension Register ......................................................... 14-33 XRA2 Cursor 1 Base Address Low Register ........................................................ 14-33 XRA3 Cursor 1 Base Address High Register ....................................................... 14-34 XRA4 Cursor 1 X-Position Low Register .............................................................. 14-34 XRA5 Cursor 1 X-Position High Register .............................................................14-35 XRA6 Cursor 1 Y-Position Low Register .............................................................. 14-35 XRA7 Cursor 1 Y-Position High Register .............................................................14-36 XRA8 Cursor 2 Control Register ..........................................................................14-37 XRA9 Cursor 2 Vertical Extension Register ......................................................... 14-38 XRAA Cursor 2 Base Address Low Register ........................................................ 14-38 XRAB Cursor 2 Base Address High Register ....................................................... 14-39 XRAC Cursor 2 X-Position Low Register .............................................................. 14-39 XRAD Cursor 2 X-Position High Register .............................................................14-40 XRAE Cursor 2 Y-Position Low Register .............................................................. 14-40 XRAF Cursor 2 Y-Position High Register .............................................................14-41 XRC0 Dot Clock 0 VCO M-Divisor Register ......................................................... 14-41 XRC1 Dot Clock 0 VCO N-Divisor Register .......................................................... 14-42 XRC3 Dot Clock 0 Divisor Select Register ........................................................... 14-43 XRC4 Dot Clock 1 VCO M-Divisor Register ......................................................... 14-45 XRC5 Dot Clock 1 VCO N-Divisor Register .......................................................... 14-45
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Chapter 14 Extension Registers (Continued)
XRC7 XRC8 XRC9 XRCB XRCC XRCD XRCE XRCF XRD0 XRD1 XRD2 XRE0-XRE3 XRE4-XREF XRF8-XRFC Dot Clock 1 Divisor Select Register ........................................................... 14-46 Dot Clock 2 VCO M-Divisor Register ......................................................... 14-48 Dot Clock 2 VCO N-Divisor Register .......................................................... 14-48 Dot Clock 2 Divisor Select Register ........................................................... 14-49 Memory Clock VCO M-Divisor Register ..................................................... 14-51 Memory Clock VCO N-Divisor Register ..................................................... 14-51 Memory Clock Divisor Select Register ....................................................... 14-52 Clock Configuration Register ..................................................................... 14-53 Powerdown Control Register ..................................................................... 14-54 Power Conservation Control Register ........................................................ 14-55 2KHz Down Counter Register .................................................................... 14-55 Software Flag Registers ............................................................................. 14-56 Software Flag Registers ............................................................................. 14-56 Test Registers ............................................................................................ 14-57
Chapter 15 Flat Panel Registers
Introduction ................................................................................................................................ 15-1 FR00 Pipeline Feature Register ............................................................................. 15-3 FR01 Pipeline Enable & Timing Select Register .................................................... 15-4 FR02 Output Enable & Assignment Register ......................................................... 15-6 FR03 Output Blanking Register ............................................................................. 15-7 FR04 Panel Power Sequencing Delay Register .................................................... 15-8 FR05 Miscellaneous Control Register ................................................................... 15-9 FR06 Output Disable State Register .................................................................... 15-10 FR08 FP Pin Polarity Register ............................................................................. 15-11 FR0A Programmable Output Drive Register ........................................................ 15-12 FR0B FP Pin Control 1 Register .......................................................................... 15-13 FR0C Pin Control 2 Register ................................................................................ 15-14 FR0F Activity Timer Control Register ................................................................... 15-15 FR10 FP Format 0 Register ................................................................................. 15-16 FR11 FP Format 1 Register ................................................................................. 15-18 FR12 FP Format 2 Register ................................................................................ 15-20 FR13 FP Format 3 Register ................................................................................ 15-22 FR16 FRC Option Select Register ....................................................................... 15-23 FR17 Polynomial FRC Control Register .............................................................. 15-24 FR18 FP Text Mode Control Register .................................................................. 15-24 FR19 Blink Rate Control Register ........................................................................ 15-25 FR1A STN-DD Buffering Control Register ........................................................... 15-26 FR1E M (ACDCLK) Control Register ................................................................... 15-26 FR1F Diagnostic Register .................................................................................... 15-27 FR20 FP Horizontal Panel Display Size LSB Register ........................................ 15-28 FR21 FP Horizontal Sync Start LSB Register ...................................................... 15-28 FR22 FP Horizontal Sync End Register ............................................................... 15-29 FR23 FP Horizontal Total LSB Register .............................................................. 15-29 FR24 FP HSync (LP) Delay LSB Register ........................................................... 15-30 FR25 FP Horizontal Overflow 1 Register ............................................................. 15-30 FR26 FP Horizontal Overflow 2 Register ............................................................. 15-31 FR27 FP HSync (LP) Width and Disable Register ............................................... 15-31 FR30 FP Vertical Panel Size LSB Register ......................................................... 15-32 FR31 FP Vertical Sync Start LSB (FR31) Register .............................................. 15-32 FR32 FP Vertical Sync End Register ................................................................... 15-33 FR33 FP Vertical Total LSB Register .................................................................. 15-33 FR34 FP VSync (FLM) Delay LSB Register ........................................................ 15-34
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Chapter 15 Flat Panel Registers (Continued)
FR35 FR36 FR37 FR40 FR41 FR48 FR49-4C FR4D FR4E FR70 FR71 FR72 FR73 FR74 FP Vertical Overflow 1 Register ................................................................. 15-34 FP Vertical Overflow 2 Register ................................................................. 15-35 FP VSync (FLM) Disable Register .............................................................15-35 Horizontal Compensation Register ............................................................ 15-36 Horizontal Stretching Register ...................................................................15-38 Vertical Compensation Register ................................................................. 15-39 Text Mode Vertical Stretching Register ...................................................... 15-40 Vertical Line Replication Register .............................................................. 15-40 Selective Vertical Stretching Disable Register ........................................... 15-41 TMED Red Seed Register ..........................................................................15-42 TMED Green Seed Register ...................................................................... 15-42 TMED Blue Seed Register ......................................................................... 15-42 TMED Control Register .............................................................................. 15-43 TMED2 Control Register ............................................................................ 15-44
Chapter 16 Multimedia Registers
Introduction ................................................................................................................................ 16-1 MR00 Module Capability Register .......................................................................... 16-2 MR01 Secondary Capability Register .....................................................................16-2 MR02 Capture Control 1 Register .......................................................................... 16-3 MR03 Capture Control 2 Register .......................................................................... 16-4 MR04 Capture Control 3 Register .......................................................................... 16-5 MR05 Capture Control 4 Register .......................................................................... 16-6 MR06 Capture Memory Address PTR1 Low Register ............................................16-7 MR07 Capture Memory Address PTR1 Mid Register ............................................. 16-7 MR08 Capture Memory Address PTR1 High Register ........................................... 16-7 MR09 Capture Memory Address PTR2 Low Register ............................................16-8 MR0A Capture Memory Address PTR2 Mid Register ............................................. 16-8 MR0B Capture Memory Address PTR2 High Register ........................................... 16-8 MR0C Capture Line Memory Storage Width Register ............................................16-9 MR0E Capture Window X-LEFT Low Register ....................................................... 16-9 MR0F Capture Window X-LEFT High Register ...................................................... 16-9 MR10 Capture Window X-RIGHT Low Register ................................................... 16-10 MR11 Capture Window X-RIGHT High Register .................................................. 16-10 MR12 Capture Window Y-TOP Low Register ....................................................... 16-11 MR13 Capture Window Y-TOP High Register ...................................................... 16-11 MR14 Capture Window Y-BOTTOM Low Register ............................................... 16-12 MR15 Capture Window Y-BOTTOM High Register .............................................. 16-12 MR16 H-SCALE Register ..................................................................................... 16-13 MR17 V-SCALE Register ..................................................................................... 16-13 MR18 Capture Frame/Field Drop Count Register ................................................16-13 MR1E/9E Playback Control 1 Register ....................................................................... 16-14 MR1F/9F Playback Control 2 Register ....................................................................... 16-16 MR20/A0 Playback Control 3 Register ....................................................................... 16-17 MR21/A1 Double Buffer Status Register .................................................................... 16-18 MR22/A2 Playback Memory Address PTR1 Low Register ........................................ 16-20 MR23/A3 Playback Memory Address PTR1 Mid Register ......................................... 16-20 MR24/A4 Playback Memory Address PTR1 High Register ....................................... 16-20 MR25/A5 Playback Memory Address PTR2 Low Register ........................................ 16-21 MR26/A6 Playback Memory Address PTR2 Mid Register ......................................... 16-21 MR27/A7 Playback Memory Address PTR2 High Register ....................................... 16-21 MR28/A8 Playback Line Memory Fetch Width Register ............................................ 16-22 MR2A/AA Playback Window X-LEFT Low Register ................................................... 16-23
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Chapter 16 Multimedia Registers (Continued)
MR2B/AB MR2C/AC MR2D/AD MR2E/AE MR2F/AF MR30/B0 MR31/B1 MR32/B2 MR33/B3 MR34/B4 MR3C/BC MR3D/BD-3F/BF MR40/C0-42/C2 MR43 MR44 Playback Window X-LEFT High Register ................................................... 16-23 Playback Window X-RIGHT Low Register ................................................. 16-24 Playback Window X-RIGHT High Register ................................................ 16-24 Playback Window Y-TOP Low Register ..................................................... 16-25 Playback Window Y-TOP High Register .................................................... 16-25 Playback Window Y-BOTTOM Low Register ............................................. 16-26 Playback Window Y-BOTTOM High Register ............................................ 16-26 H-ZOOM Register ...................................................................................... 16-27 V-ZOOM Register ...................................................................................... 16-27 Playback Line Display Width Register ....................................................... 16-28 Color Key Control Register ........................................................................ 16-29 Color Key Registers ................................................................................... 16-30 Color Key Mask Registers .......................................................................... 16-31 Display Scanline Count Low ...................................................................... 16-32 Display Line Count Low ............................................................................. 16-32
Chapter 17 BitBLT Registers
Introduction ................................................................................................................................ 17-1 BR00 Source and Destination Span Register ........................................................ 17-2 BR01 Pattern/Source Expansion Background Color & Transparency Key Register 17-3 BR02 Pattern/Source Expansion Foreground Color Register ................................ 17-4 BR03 Monochrome Source Control Register ......................................................... 17-5 BR04 BitBLT Control Register ............................................................................... 17-7 BR05 Pattern Address Register ........................................................................... 17-12 BR06 Source Address Register ........................................................................... 17-13 BR07 Destination Address Register ..................................................................... 17-14 BR08 Destination Width & Height Register .......................................................... 17-15 BR09 Source Expansion Background Color & Transparency Key Register ........ 17-16 BR0A Source Expansion Foreground Color Register .......................................... 17-17
Chapter 18 Memory-Mapped Wide Extension Registers
Introduction ................................................................................................................................ 18-1 ER00 Central Interrupt Control Register ................................................................ 18-2 ER01 Central Interrupt Pending/Acknowledge Register ........................................ 18-3 ER03 Miscellaneous Function Register ................................................................. 18-5
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Appendix A Display Modes
Introduction ................................................................................................................................. A-1
Appendix B Clock Generation
Introduction ................................................................................................................................. B-1 Clock Synthesizer ....................................................................................................................... B-1 Dot Clock (DCLK) ....................................................................................................................... B-1 Memory Clock (MCLK) ............................................................................................................... B-1 PLL Parameters ......................................................................................................................... B-2 Programming the Clock Synthesizer .......................................................................................... B-3 DCLK Programming ................................................................................................................... B-3 MCLK Programming ................................................................................................................... B-3 Programming Constraints ........................................................................................................... B-4 Programming Example ............................................................................................................... B-4 PCB Layout Considerations ....................................................................................................... B-5 Display Memory Bandwidth ........................................................................................................ B-7 STN-DD Panel Buffering ............................................................................................................ B-8 Horizontal and Vertical Clocking ................................................................................................ B-9
Appendix C Panel Power Sequencing
Introduction ................................................................................................................................. C-1
Appendix D Hardware Cursor and Pop Up Window
Introduction ................................................................................................................................. D-1 Basic Cursor Configuration ........................................................................................................ D-1 Base Address for Cursor Data ................................................................................................... D-2 Cursor Vertical Extension ........................................................................................................... D-2 Cursor Colors ............................................................................................................................. D-2 Cursor Positioning ...................................................................................................................... D-3 Cursor Modes ............................................................................................................................. D-3 32x32x2bpp & 64x64x2bpp AND/XOR Pixel Plane Modes ........................................................ D-4 64x64x2bpp 4-Color Mode ......................................................................................................... D-6 64x64x2bpp 3-Color and Transparency Mode ........................................................................... D-7 128x128x1bpp 2-Color Mode ..................................................................................................... D-8 128x128x1bpp 1-Color and Transparency Mode ....................................................................... D-9
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Appendix E BitBLT Operation
Introduction ..................................................................................................................................E-1 Color Depth Configuration and Color Expansion ........................................................................E-2 Graphics Data Size Limitations ...................................................................................................E-3 Bit-Wise Operations ....................................................................................................................E-3 Per-Pixel Write Masking ..............................................................................................................E-7 When the Source and Destination Locations Overlap .................................................................E-8 Contiguous vs. Discontiguous Graphics Data ...........................................................................E-12 Source Data ..............................................................................................................................E-13 Monochrome Source Data ........................................................................................................E-14 Pattern Data ..............................................................................................................................E-14 Destination Data ........................................................................................................................E-17 BitBLT Programming Examples ................................................................................................E-18 Pattern Fill -- A Very Simple BitBLT ..........................................................................................E-18 Drawing Characters Using a Font Stored in System Memory ...................................................E-20
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List of Figures
Figure 1-1: Dual-Pipe Simultaneous Mode ..................................................................................... 1-1 Figure 1-2: Independent Images .................................................................................................... 1-2 Figure 1-3: Virtual Desktop ............................................................................................................. 1-2 Figure 3-1: AC Test Timing ............................................................................................................ 3-3 Figure 3-2: Reference Clock Timing ............................................................................................... 3-4 Figure 3-3: Reset Timing ................................................................................................................ 3-5 Figure 3-4: PCI Bus Frame Timing ................................................................................................. 3-6 Figure 3-5: PCI Bus Stop Timing .................................................................................................... 3-6 Figure 3-6: PCI BIOS ROM Timing ................................................................................................ 3-7 Figure 3-7: Video Data Port Timing ................................................................................................ 3-7 Figure 3-8: Panel Output Timing .................................................................................................... 3-8 Figure 4-1: 256+16-Contact Ball Grid Array ................................................................................... 4-1 Figure 4-2: 256 Ball - Mini Ball Grid Array ...................................................................................... 4-2 Figure B-1: PLL Elements ............................................................................................................. B-2 Figure E-1: Block Diagram and Data Paths of the BitBLT Engine ................................................. E-1 Figure E-2: Block Diagram and Data Paths of the BitBLT Engine ................................................. E-7 Figure E-3: Source Corruption in BitBLT with Overlapping Source and Destination Locations .... E-8 Figure E-4: Correctly Performed BitBLT with Overlapping Source and Destination Locations ... E-10 Figure E-5: Suggested Starting Points for Possible Source and Destination Overlap Situations E-11 Figure E-6: On-Screen Single 6-Pixel Line in the Frame Buffer .................................................. E-12 Figure E-7: On-Screen 6x4 Array of Pixels in the Frame Buffer .................................................. E-13 Figure E-8: Pattern Data .............................................................................................................. E-15 Figure E-9: Monochrome Pattern Data -- Occupies a Single Quadword ..................................... E-15 Figure E-10: 8bpp Pattern Data -- Occupies 64 Bytes (8 Quadwords) ....................................... E-15 Figure E-11: 16bpp Pattern Data -- Occupies 128 Bytes (16 Quadwords) ................................. E-16 Figure E-12: 24bpp Pattern Data -- Occupies 256 Bytes (32 Quadwords) ................................. E-16 Figure E-13: On-Screen Destination for Example Pattern Fill BitBLT ......................................... E-18 Figure E-14: Pattern Data for Example Pattern Fill BitBLT ......................................................... E-19 Figure E-15: Results of Example Pattern Fill BitBLT ................................................................... E-20 Figure E-16: On-Screen Destination for Example Character Drawing BitBLT ............................ E-21 Figure E-17: Source Data in System Memory for Example Character Drawing BitBLT .............. E-21 Figure E-18: Results of Example Character Drawing BitBLT ...................................................... E-23
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List of Tables
Table 2-1: Pin Diagram, B69030 Ball Grid Array (Top View) ....................................................... 2-1 Table 2-2: Pin Diagram, B69030 Ball Grid Array (Bottom View).................................................. 2-2 Table 2-3: Pin Diagram, M69030 Mini Ball Grid Array (Top View) ............................................... 2-3 Table 2-4: Pin Diagram, M69030 Mini Ball Grid Array (Bottom View).......................................... 2-4 Table 3-1: Absolute Maximum Conditions ................................................................................... 3-1 Table 3-2: Normal Operating Conditions ..................................................................................... 3-1 Table 3-3: DAC Characteristics ................................................................................................... 3-1 Table 3-4: DC Characteristics...................................................................................................... 3-2 Table 3-5: DC Drive Characteristics ............................................................................................ 3-2 Table 3-6: AC Test Conditions: .................................................................................................. 3-3 Table 3-7: AC Timing Characteristics - Reference Clock............................................................. 3-4 Table 3-8: AC Timing Characteristics - Clock Generator ............................................................ 3-4 Table 3-9: AC Timing Characteristics - Reset ............................................................................. 3-4 Table 3-10: AC Timing Characteristics - PCI Bus Frame (CLK=33MHz)..................................... 3-5 Table 3-11: AC Timing Characteristics - PCI Bus Stop (CLK=33MHz) ........................................ 3-6 Table 3-12: AC Timing Characteristics - PC BIOS ROM ............................................................. 3-6 Table 3-13: AC Timing Characteristics - Video Data Port ............................................................ 3-7 Table 3-14: AC Timing Characteristics - Panel Output Timing..................................................... 3-7 Table 3-15: AC Timing Characteristics - A.G.P. 1x AC Timing Parameters ................................. 3-8 Table 5-1: Lower Memory Map .................................................................................................... 5-2 Table 5-2: I/O and Sub-Addressed Register Map ........................................................................ 5-2 Table 5-3: Sub-Indexing Indices and Data Ports ......................................................................... 5-4 Table 5-4: I/O Space Register Shadowing................................................................................... 5-6 Table 5-5: Upper Memory Map -- Dual-Pipe Mapping ............................................................... 5-10 Table 5-6: Upper Memory Map -- Multiple-Endian Mapping ...................................................... 5-10 Table 6-1: PCI Configuration Registers ....................................................................................... 6-1 Table 6-2: General Control & Status Registers ............................................................................ 6-2 Table 6-3: CRT Controller Registers............................................................................................ 6-3 Table 6-4: Sequencer Register .................................................................................................... 6-4 Table 6-5: Graphics Controller Registers..................................................................................... 6-4 Table 6-6: Attribute Controller Register ....................................................................................... 6-4 Table 6-7: Palette Registers ........................................................................................................ 6-5 Table 6-8: Extension Register...................................................................................................... 6-5 Table 6-9: Flat Panel Registers ................................................................................................... 6-7 Table 6-10: Multimedia Registers ................................................................................................ 6-8 Table 6-11: BitBLT Registers ....................................................................................................... 6-9 Table 6-12: Memory-mapped Wide Extension Registers ............................................................ 6-9
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List of Tables (Continued)
Table 7-1: PCI Configuration Registers ....................................................................................... 7-1 Table 8-1: General Control and Status Registers ........................................................................ 8-1 Table 9-1: CRT Controller Registers............................................................................................ 9-1 Table 10-1: Sequencer Registers .............................................................................................. 10-1 Table 11-1: Graphics Controller Registers ................................................................................. 11-1 Table 12-1: Attribute Controller Registers.................................................................................. 12-1 Table 13-1: Palette Registers .................................................................................................... 13-1 Table 14-1: Extension Registers................................................................................................ 14-1 Table 15-1: Flat Panel Registers ............................................................................................... 15-1 Table 16-1: Multimedia Registers .............................................................................................. 16-1 Table 16-2: Color Key bit assignments: .................................................................................. 16-31 Table 17-1: BitBLT Registers ..................................................................................................... 17-1 Table 18-1: Memory-Mapped Wide Extension Registers .......................................................... 18-1 Table D-1: Memory Organization 32x32x2bpp AND/XOR Pixel Plane Mode............................. Table D-2: Memory Organization 64x64x2bpp AND/XOR Pixel Plane Mode............................. Table D-3: Pixel Data 32x32x2bpp and 64x64x2bpp AND/XOR Pixel Plane Modes ................. Table D-4: Memory Organization 64x64x2bpp 4-Color Mode .................................................... Table D-5: Pixel Data 64x64x2bpp 4-Color Mode ...................................................................... Table D-6: Memory Organization 64x64x2bpp 3-Color & Transparency Mode .......................... Table D-7: Pixel Data 64x64x2bpp 3-Color & Transparency Mode ............................................ Table D-8: Memory Organization 128x128x1bpp 2-Color Mode ................................................ Table D-9: Pixel Data 128x128x1bpp 2-Color Mode .................................................................. Table D-10: Memory Organization 128x128x1bpp 1-Color & Transparency Mode .................... Table D-11: Pixel Bit Definitions 128x128x1bpp 1-Color & Transparency Mode ........................ D-4 D-5 D-5 D-6 D-6 D-7 D-7 D-8 D-8 D-9 D-9
Table E-1: Bit-Wise Operations and 8-bit Codes (00 - 5F) ......................................................... E-4 Table E-2: Bit-Wise Operations and 8-bit Codes (60 - BF)......................................................... E-5 Table E-3: Bit-Wise Operations and 8-bit Codes (C0 - FF) ........................................................ E-6
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Introduction / Overview
1-1
Chapter 1 Introduction / Overview
The 69030 graphics accelerator is the newest product in the family of portable graphic accelerators that embeds 4 megabytes of high performance Synchronous Dynamic Random Access Memory (SDRAM) technology for the graphics frame buffer. Based on the proven HiQVideoTM embedded graphics accelerator core, the 69030 graphics accelerator combines state-of-the-art flat panel controller capabilities with low power, high performance embedded memory. The result is a high performance, low power, and highly integrated solution for mainstream embedded notebooks and industrial PCs.
High Performance Embedded Memory
The 69030 graphics accelerator is the second generation of the HiQVideoTM family to embed a high performance SDRAM frame buffer by using leading edge embedded SDRAM memory and graphics controller logic on the same die. The 69030 graphics accelerator delivers uncompromising performance while at the same time consuming much less power than a discrete solution. The embedded 4MB SDRAM supports 83MHz operations and provides up to 664MB/s frame buffer bandwidth. This increased bandwidth and memory size also allows more flexibility in the graphics functions intensely used in Graphics User Interfaces (GUIs) such as Microsoft=Windows(R).
Dual Independent Display
The 69030 graphics accelerator carries dual independent display output pipelines, allowing it to make use of the multiple display support expected in upcoming operating systems. The two pipelines can drive two displays with differing timings and with either the same or different images. Having 4MB SDRAM and up to 664MB/s frame buffer bandwidth, the 69030 graphics accelerator enables dual display support up to 1280x1024, 256 color at 60Hz. There are three different modes that can be supported with the 69030 graphics accelerator's dual pipeline architecture:
Dual-Pipe Simultaneous Mode
* * Same image on both displays Each display can be operated at its optimum timing
Panel 8x6x16 @ 60 Hz
CRT 8x6x16 @ 75 Hz
Figure 1-1: Dual-Pipe Simultaneous Mode
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Introduction / Overview
Dual-Pipe Mosaic Mode
* Independent Images - Two completely different images on each display - Each display can be configured at its optimum resolution/timing
Panel 8x6x24 @ 60 Hz
CRT 10x7x16 @ 75 Hz
Figure 1-2: Independent Images * Virtual Desktop - Single desktop spans across two displays
Figure 1-3: Virtual Desktop
Single-Pipe Mode
* * Normal Mode - Single display device with a single graphics pipeline Simultaneous Mode - Single graphics pipeline, dual display, single timing
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Introduction / Overview
1-3
Dual Video Accelerator Engines
To enable true dual independent display, two multimedia engines are implemented in the 69030 graphics accelerator to provide video acceleration for both display pipelines. These engines support on-the-fly data conversion from YUV 4:2:2 to 24-bit RGB format, horizontal/vertical interpolation, and color key video overlay. The 69030 graphics accelerator also provides flexibility in configuring the two engines. Depending upon the dual display operating mode and application requirements, each engine can be programmed to provide dedicated video acceleration support for each display pipeline or both engines can be programmed to support acceleration for either one of the pipelines.
HiQColorTM Technology
The 69030 graphics accelerator integrates breakthrough HiQColorTM=technology. Based on the CHIPS proprietary Temporal Modulated Energy Distribution (TMED) algorithm, HiQColor technology is a unique process that allows the display of 16.7 million true colors on STN panels without using Frame Rate Control (FRC) or dithering. In addition, TMED also reduces the need for the panel tuning associated with current FRC-based algorithms. Independent of panel response, the TMED algorithm eliminates all of the flaws (such as shimmer, Mach banding, and other motion artifacts) normally associated with dithering and FRC. Combined with the new fast response, high-contrast, and low-crosstalk technology found in new STN panels, HiQColor technology enables the kind of display quality and color fidelity previously only available with TFT technology.
Acceleration for All Panels and All Modes
The 69030 graphics engine is designed to support high performance graphics and video acceleration for all supported display resolutions, display types, and color modes. There is no compromise in performance when operating in 8, 16, or 24 bpp color modes, allowing true acceleration while displaying up to 16.7M colors. The 69030 graphics engine boosts the 2D performance through specialized hardware, which accelerates the most frequently used 2D GUI operations. This acceleration is supported in all graphics modes up to 1600x1200* and all color depths for both pipelines to support the dual display function. *Up to 16bpp
Television NTSC/PAL Flicker Free Output and Underscan
The 69030 graphics accelerator uses a flicker reduction process which makes text of all fonts and sizes readable by reducing the flicker and jumping lines on the display. To accomplish this, the 69030 graphics accelerator uses a line buffer and digital filters to average adjacent vertical lines for odd/even display. The chip also uses both horizontal and vertical interpolation to make both graphics and text appear "smooth" on the television. This process reduces the effect of flicker in the NTSC/PAL mode. In order to prevent panning or the loss of data vertically on the television screen, the 69030 graphics accelerator uses a vertical reduction line dropping interval process by which the entire on-screen data can be displayed for 640x480 (NTSC) resolution and 800x600 (PAL) resolution.
HiQVideoTM Capture/Playback Support
The 69030 graphics accelerator implements a variety of features to deliver high quality, full screen, full frame-rate video capture playback for MPEG1, MPEG2, V-CD and DVD by using the independent multimedia capture and display system on-chip. The capture system places data in display memory (usually off screen) and the display system places the data in a window on the screen. The capture engine can receive data from either the system bus or from the ZV enabled video port in either RGB or YUV format. The input data can also be scaled down before storage in display memory. In order to improve the video playback quality, the 69030 graphics accelerator continuously scales video data with horizontal and vertical interpolation. Capture of input data may also be double buffered for smoothing and to prevent image tearing resulting from the display of an unfinished captured frame or field picture. To
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Introduction / Overview
enable the VPE kernal transport mode and video capture/playback auto flipping the 69030 graphics accelerator provides a hardware interrupt pin, which can be programmed to activate at either display vertical sync or video capture vertical sync signal. To better support MPEG2 (DVD) video decompression, the 69030 graphics accelerator includes a line buffer to directly support the native format of MPEG2 data of 720 pixels wide. The capture engine also supports image mirroring and rotation for camera support. This feature is important for applications such as video teleconferencing because it allows the image movements to appear on the display as it actually occurs. The image and movement is not a mirror image of what is actually taking place. The display system can independently place either RGB or YUV data from anywhere in frame buffer memory into an on-screen window which can be any size and located at any pixel boundary. Since YUV data is converted to RGB "on-the-fly" on output, the video data can be stored in the frame buffer in its native YUV format, thus enabling efficient usage of the 4MByte embedded frame buffer while providing excellent playback display quality. Non-rectangular windows are supported via color keying. The data can be fractionally zoomed on output up to 8x to fit the on-screen window and can be horizontally and vertically interpolated. Interlaced and noninterlaced data are both supported in the capture and display systems.
Versatile Panel Support
The HiQVideo family supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD), standard and high-resolution, passive STN and active matrix TFT/MIM LCD, and EL panels. With HiQColor technology, up to 256 gray scales are supported on passive STN LCDs. Up to 16.7M different colors can be displayed on passive STN LCDs and up to 16.7M colors on 24-bit active matrix LCDs. The 69030 graphics accelerator offers a variety of programmable features to optimize display quality. Horizontal and vertical stretching capabilities are also available for both text and graphics modes for optimal display of VGA text and graphics modes on 800x600, 1024x768 and 1280x1024 panels.
Integrated RAMDAC and Clock Synthesizer
The 69030 graphics accelerator contains three complete phase-locked loops (PLLs) to synthesize the two internal dot clocks (DCLK) for the display pipelines and memory clock (MCLK) from an externally supplied reference frequency. The maximum dot clock supported is 170 MHz and the maximum memory clock supported by the embedded 4MB of SDRAM is 83MHz, thereby allowing support of resolutions up to 1600x1200x16bpp at 60Hz refresh.
Low Power Consumption
The 69030 graphics accelerator uses a variety of advanced graphics power management features including ACPI compliancy to reduce power consumption of the sub-system and to extend battery life. The 69030 graphics accelerator internal logic bus and panel interfaces are optimized to operate at 3.3 volts. For additional power savings, the embedded memory subsystem voltage is stepped-down internally to operate at 2.5V.
Software Compatibility / Flexibility
The HiQVideo controllers are fully compatible with the VGA standard at both the register and BIOS levels. Intel and third-party vendors supply a fully VGA compatible BIOS, end-user utilities and drivers for common application programs.
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Pin Descriptions
2-1
Chapter 2 Pin Descriptions
Introduction
Chapter 2 describes the pin configuration for the B69030 and M69030 Dual HiQVideo Accelerators.
B69030 Pin Diagram, Top View
Table 2-1: A 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
CFG4
Pin Diagram, B69030 Ball Grid Array (Top View) C
N/C
B
CFG2
D
N/C
E
N/C
F
N/C
G
N/C
H
N/C
J
N/C
K
N/C
L
RMA17
M
N/C
N
N/C
P
N/C
R
N/C
T
N/C
U
VP1
V
VP6
W
VP10
Y
RSVD
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
CFG6
CFG5
CFG1
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RMA16
N/C
N/C
N/C
N/C
VP2
VP5
VP9
VP11
VP14
N/C
CFG7
CFG3
CFG0
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VP0
VP4
VP8
VP13
VP15
VCLK
RMA2
N/C
CFG8
TMD0
N/C
N/C
MEMGND MEMVCC
N/C
N/C
N/C
N/C
MEMVCC MEMGND
VP3
VP7
VP12
PCLK
HREF
P33
RMA4
RMA1
N/C
CFG9
RSVD
VREF
P34
P31
RMA7
RMA5
RMA3
RMA0
P35
P32
P30
P28
RMA10
RMA8
RMA6
MEMGND
GND
P29
P27
P25
RMA14
RMA11
RMA9
MEMVCC
IOVCC
P26
P24
P21
TMD1
RMA15
RMA13
RMA12
12 11 10 9
GND GND GND GND J
GND GND GND GND K
GND GND GND GND L
RGND RGND RGND RGND M
P23
P22
CORVCC
P20
N/C
N/C
N/C
N/C
P16
P19
P18
P17
N/C
CFG10
CFG11
N/C
P15
P12
P13
P14
CFG12
CFG13
CFG15
CORVCC
P7
P8
P10
P11
CFG14
RMD0
RMD2
RSVD
IOVCC
P4
P6
P9
RMD1
RMD3
RMD5
GND
GND
P1
P3
P5
RMD4
RMD6
ROMOE#
RSVD
ENABKL
M
P0
P2
RMD7
RSVD
RSVD
DCKVCC
DACVCC ENAVDD
FLM
SHFCLK
INT#
DCKGND DCKVCC
RSVD
STNDBY#
AD30
GND
IOVCC
AD20
TRDY#
DEVSEL#
AD13
IOVCC
GND
AD2
GPIO1
DDC CLK HSYNC
GREEN
ENAVEE
LP
DCKGND MCKVCC
REFCLK
RSVD
AD31
AD27
AD24
AD23
AD19
C/BE2#
SERR#
AD14
AD10
C/BE0#
AD5
AD1
DDC DATA VSYNC
BLUE
RED
MCKGND
DCLKIN
RSVD
BUSCLK
AD29
AD25
IDSEL
AD21
AD17
FRAME#
PERR#
C/BE1#
AD12
AD9
AD7
AD3
AD0
RSET
DACGND
RSVD
MCLKIN
RESET#
AD28
AD26
C/BE3#
AD22
AD18
AD16
IRDY#
STOP#
PAR
AD15
AD11
AD8
AD6
AD4
GPIO0
IOVCC
RGND
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
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2-2
Pin Descriptions
B69030 Pin Diagram, Bottom View
Table 2-2: Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RSVD
Pin Diagram, B69030 Ball Grid Array (Bottom View) V
VP6
W
VP10
U
VP1
T
N/C
R
N/C
P
N/C
N
N/C
M
N/C
L
RMA17
K
N/C
J
N/C
H
N/C
G
N/C
F
N/C
E
N/C
D
N/C
C
N/C
B
CFG2
A
CFG4
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VP14
VP11
VP9
VP5
VP2
N/C
N/C
N/C
N/C
RMA16
N/C
N/C
N/C
N/C
N/C
N/C
N/C
CFG1
CFG5
CFG6
VCLK
VP15
VP13
VP8
VP4
VP0
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
CFG0
CFG3
CFG7
N/C
P33
HREF
PCLK
VP12
VP7
VP3
MEMGND MEMVCC
N/C
N/C
N/C
N/C
MEMVCC MEMGND
N/C
N/C
TMD0
CFG8
N/C
RMA2
P31
P34
VREF
RSVD
CFG9
N/C
RMA1
RMA4
P28
P30
P32
P35
RMA0
RMA3
RMA5
RMA7
P25
P27
P29
GND
MEMGND
RMA6
RMA8
RMA10
P21
P24
P26
IOVCC
MEMVCC
RMA9
RMA11
RMA14
P20
CORVCC
P22
P23
12 11 10 9
RGND
GND
GND
GND
RMA12
RMA13
RMA15
TMD1
P17
P18
P19
P16
RGND
GND
GND
GND
N/C
N/C
N/C
N/C
P14
P13
P12
P15
RGND
GND
GND
GND
N/C
CFG11
CFG10
N/C
P11
P10
P8
P7
RGND
GND
GND
GND
CORVCC
CFG15
CFG13
CFG12
P9
P6
P4
IOVCC
M
L
K
J
RSVD
RMD2
RMD0
CFG14
P5
P3
P1
GND
GND
RMD5
RMD3
RMD1
P2
P0
M
ENABKL
RSVD
ROMOE#
RMD6
RMD4
SHFCLK
FLM
ENAVDD DACVCC
DCKVCC
RSVD
RSVD
RMD7
LP
ENAVEE
GREEN
DDC CLK HSYNC
GPIO1
AD2
GND
IOVCC
AD13
DEVSEL#
TRDY#
AD20
IOVCC
GND
AD30
STNDBY#
RSVD
DCKVCC DCKGND
INT#
RED
BLUE
DDC DATA VSYNC
AD1
AD5
C/BE0#
AD10
AD14
SERR#
C/BE2#
AD19
AD23
AD24
AD27
AD31
RSVD
REFCLK
MCKVCC DCKGND
DACGND
RSET
AD0
AD3
AD7
AD9
AD12
C/BE1#
PERR#
FRAME#
AD17
AD21
IDSEL
AD25
AD29
BUSCLK
RSVD
DCLKIN
MCKGND
RGND
IOVCC
GPIO0
AD4
AD6
AD8
AD11
AD15
PAR
STOP#
IRDY#
AD16
AD18
AD22
C/BE3#
AD26
AD28
RESET#
MCLKIN
RSVD
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
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Pin Descriptions
2-3
M69030 Pin Diagram, Top View
Table 2-3: A 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
N/C N/C
Pin Diagram, M69030 Mini Ball Grid Array (Top View) B
N/C N/C
C
N/C N/C
D
N/C N/C
E
N/C N/C
F
N/C N/C
G
N/C MEM GND MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC GND
H
N/C MEM GND GND
J
N/C MEM GND GND
K
N/C MEM VCC GND
L
N/C GND
M
VP3 VP6
N
N/C VP0
P
VP2 VP5
R
RMA17 VP8
T
RMA16 VP1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TMD0
N/C
N/C
MEM GND N/C
MEM GND N/C
MEM GND N/C
VP7
VP13
VP4
VP10
VP12
VP9
CFG0
CFG4
N/C
GND
GND
IOVCC
VP15
HREF
VP11
RSVD
VCLK
VP14
CFG3
CFG9
CFG5
CFG6
CFG1
CFG2
GND
GND
IOVCC
IOVCC
P32
PCLK
P35
P34
VREF
CFG8
RMA4
RMA0
RMA1
RMA2
CFG7
GND
GND
IOVCC
IOVCC
P28
P33
P31
P29
P30
RMA3
RMA9
RMA5
RMA7
RMA8
MEM VCC GND
GND
MEM GND GND
P21
P22
P24
P26
P25
P23
P27
RMA6
RMA14 CFG12 TMD1
RMA10
RMA11
RMA13 CFG11 RMD0 CFG13 RMD5
GND
P15
MEM VCC P9
P20
IOVCC
P19
P17
P18
RMA12
N/C
COR VCC RMD3
GND
IOVCC
GND
IOVCC
IOVCC
P11
P13
COR VCC P8
P14
P16
RMA15 CFG10 RMD1 CFG14 RSVD
RMD2 CFG15 RMD6
COR VCC RMD4
GND
IOVCC
IOVCC
COR VCC C/BE1#
HSYNC
FLM
P4
P6
P10
P12
RMD7
DCK VCC MCLKIN
GND
GND
GND
RED
IOVCC
M
P1
P2
P5
P7
INT#
DCK GND N/C
N/C
AD29
AD28
AD23
DEV SEL# SERR#
AD10
AD5
DAC GND AD1
ENA VDD DDCK
LP
P0
P3
ROMOE#
DCK VCC REF CLK N/C
MCK VCC AD31
RESET#
AD25
AD21
AD17
AD14
AD7
GREEN
ENA BKL DAC VCC DDC DATA VSYNC
SHF CLK ENA VEE BLUE
DCK GND MCK GND DCLKIN
STND BY AD30
AD27
C/BE3#
AD19
FRAME#
PERR#
AD12
AD8
AD3
GPIO0 ACTI AD2
RGND
AD24
AD22
AD18
C/BE2#
TRDY#
PAR
AD13
AD9
AD6
GPIO1 32KHZ AD0
RSVD
BUS CLK
AD26
IDSEL
AD20
AD16
IRDY#
STOP#
AD15
AD11
C/BE0#
AD4
RSET
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
efmp69030 Databook
Revision 1.3 11/24/99
2-4
Pin Descriptions
M69030 Pin Diagram, Bottom View
Table 2-4: T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RMA16 VP1
Pin Diagram, M69030 Mini Ball Grid Array (Bottom View) R
RMA17 VP8
P
VP2 VP5
N
N/C VP0
M
VP3 VP6
L
N/C GND
K
N/C MEM VCC GND
J
N/C MEM GND GND
H
N/C MEM GND GND
G
N/C MEM GND MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC GND
F
N/C N/C
E
N/C N/C
D
N/C N/C
C
N/C N/C
B
N/C N/C
A
N/C N/C
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VP9
VP12
VP10
VP4
VP13
VP7
MEM GND N/C
MEM GND N/C
MEM GND N/C
N/C
N/C
TMD0
VP14
VCLK
RSVD
VP11
HREF
VP15
IOVCC
GND
GND
N/C
CFG4
CFG0
VREF
P34
P35
PCLK
P32
IOVCC
IOVCC
GND
GND
CFG2
CFG1
CFG6
CFG5
CFG9
CFG3
P30
P29
P31
P33
P28
IOVCC
IOVCC
GND
GND
CFG7
RMA2
RMA1
RMA0
RMA4
CFG8
P27
P23
P25
P26
P24
P22
P21
MEM GND GND
GND
MEM VCC GND
RMA8
RMA7
RMA5
RMA9
RMA3
P18
P17
P19
IOVCC
P20
MEM VCC P9
P15
GND
RMA13 CFG11 RMD0 CFG13 RMD5
RMA11
RMA10
RMA14 CFG12 TMD1
RMA6
P16
P14
COR VCC P8
P13
P11
IOVCC
IOVCC
GND
IOVCC
GND
COR VCC RMD3
N/C
RMA12
P12
P10
P6
P4
FLM
HSYNC
COR VCC C/BE1#
IOVCC
IOVCC
GND
COR VCC RMD4
RMD2 CFG15 RMD6
RMA15 CFG10 RMD1 CFG14 RSVD
P7
P5
P2
P1
M
IOVCC
RED
GND
GND
GND
DCK VCC MCLKIN
RMD7
P3
P0
LP
ENA VDD DDCK
DAC GND AD1
AD5
AD10
DEV SEL# SERR#
AD23
AD28
AD29
N/C
DCK GND N/C
INT#
SHF CLK ENA VEE BLUE
ENA BKL DAC VCC DDC DATA VSYNC
GREEN
AD7
AD14
AD17
AD21
AD25
RESET#
MCK VCC AD31
DCK VCC REF CLK N/C
ROMOE#
RGND
GPIO0 ACTI AD2
AD3
AD8
AD12
PERR#
FRAME#
AD19
C/BE3#
AD27
STND BY AD30
DCK GND MCK GND DCLKIN
GPIO1 32KHZ AD0
AD6
AD9
AD13
PAR
TRDY#
C/BE2#
AD18
AD22
AD24
RSET
AD4
C/BE0#
AD11
AD15
STOP#
IRDY#
AD16
AD20
IDSEL
AD26
BUS CLK
RSVD
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
efmp69030 Databook
Revision 1.3 11/24/99
Pin Descriptions
2-5
B69030 and M69030 PCI/AGP Bus Interface
BGA Pin C1 mBGA Pin Name Pin E4 RESET# Type In Active Low Powered IOVCC & GND Description Reset. This input sets all signals and registers in the chip to a known state. All outputs from the chip are tri-stated or driven to an inactive state. If STNDBY# and RESET# are active at the same time, RESET# only initializes the ENAVDD, ENAVEE and ENABKL on pin 3. The rest of the logic on the chip does not receive the reset signal and will remain uninitialized. Bus Clock. This input provides the timing reference for all PCI and AGP bus transactions. All bus inputs except RESET# are sampled on the rising edge of BUSCLK. BUSCLK may be any frequency from DC up to 33MHz for PCI, or up to 66MHz for AGP. Parity. This signal is used to maintain even parity across AD0-31 and C/BE0-3#. PAR is stable and valid one clock after the address phase. For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase (i.e., PAR has the same timing as AD0-31 but delayed by one clock). The bus master drives PAR for address and write data phases; the target drives PAR for read data phases. Cycle Frame. Driven by the current master to indicate the beginning and duration of an access. Assertion indicates a bus transaction is beginning (while asserted, data transfers continue); de-assertion indicates the transaction is in the final data phase Initiator Ready. Indicates the bus master's ability to complete the current data phase of the transaction. During a write, IRDY# indicates valid data is present on AD0-31; during a read it indicates the master is prepared to accept data. A data phase is completed on any clock when both IRDY# and TRDY# are sampled then asserted (wait cycles are inserted until this occurs). Target Ready. Indicates the target's ability to complete the current data phase of the transaction. During a read, TRDY# indicates that valid data is present on AD0-31; during a write it indicates the target is prepared to accept data. A data phase is completed on any clock when both IRDY# and TRDY# are sampled then asserted (wait cycles are inserted until this occurs). Stop. Indicates the current target is requesting the master to stop the current transaction.
D2
C1
BUSCLK
In
High
IOVCC & GND
M1
J2
PAR
I/O
High
IOVCC & GND
K2
H3
FRAME#
In
Low
IOVCC & GND
K1
H1
IRDY#
In
Low
IOVCC & GND
K4
H2
TRDY#
S/TS
Low
IOVCC & GND
L1
J1
STOP#
S/TS
Low
IOVCC & GND
Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before released, and are not driven for at least one cycle after being released by the previous device. A pull-up provided by the bus controller is used to maintain an inactive level between transactions.
efmp69030 Databook
Revision 1.3 11/24/99
2-6
Pin Descriptions
B69030 and M69030 PCI/AGP Bus Interface (continued)
BGA Pin L4 L2 mBGA Pin Name Pin J5 J3 DEVSEL# PERR# Type S/TS S/TS Active Powered Low Low IOVCC & GND IOVCC & GND Description Device Select. Indicates the current target has decoded its address as the target of the current access Parity Error. This signal reports data parity errors (except for Special Cycles where SERR# is used). The PERR# pin is Sustained Tri-state. The receiving agent will drive PERR# active two clocks after detecting a data parity error. PERR# will be driven high for one clock before being tristated as with all sustained tri-state signals. PERR# will not report status until the chip has claimed the access by asserting DEVSEL# and completing the data phase. System Error. Used to report system errors where the result will be catastrophic (address parity error, data parity errors for Special Cycle commands, etc.). This output is actively driven for a single PCI/AGP clock cycle synchronous to BCLK and meets the same setup and hold time requirements as all other bused signals. SERR# is not driven high by the chip after being asserted, but is pulled high only by a weak pull-up provided by the system. Thus, SERR# on the PCI/AGP bus may take two or three clock periods to fully return to an inactive state. Interrupt request pin.
L3
J4
SERR#
OD
Low
IOVCC & GND
A4
B5
INT#
OD
Low
IOVCC & GND
Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before released, and are not driven for at least one cycle after being released by the previous device. A pull-up provided by the bus controller is used to maintain an inactive level between transactions.
efmp69030 Databook
Revision 1.3 11/24/99
Pin Descriptions
2-7
B69030 and M69030 PCI/AGP Bus Interface (continued)
BGA Pin U2 T3 R4 T2 U1 R3 T1 R2 R1 P2 N3 P1 N2 M4 M3 N1 J1 J2 H1 J3 J4 H2 G1 H3 G3 F2 E1 F3 D1 E2 F4 E3 P3 M2 K3 F1 G2 mBGA Pin P1 M4 N2 M3 N1 L5 M2 L4 L3 L2 K5 L1 K3 K2 K4 K1 G1 H4 F2 G3 F1 G4 E2 H5 D2 F4 D1 E3 G5 F5 C2 D3 M1 J6 G2 F3 E1 Pin Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# IDSEL Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O In In In In In Active High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High Low Low Low Low High Powered IOVCC & GND Description PCI/AGP Address/Data Bus Address and data are multiplexed on the same pins. A bus transaction consists of an address phase followed by one or more data phases (both read and write bursts are allowed by the bus definition). The address phase is the clock cycle in which FRAME# is asserted (AD0-31 contain a 32-bit physical address). For I/O, the address is a byte address. For memory and configuration, the address is a DWORD address. During data phases AD0-7 contain the LSB and 24-31 contain the MSB. Write data is stable and valid when IRDY# is asserted; read data is stable and valid when TRDY# is asserted. Data transfers only during those clocks when both IRDY# and TRDY# are asserted. C/BE3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 IOVCC & GND Command Type Supported Interrupt Acknowledge Special Cycle I/O Read Y I/O Write Y -reserved-reservedMemory Read Y Memory Write Y -reserved-reservedConfiguration Read Y Configuration Write Y Memory Read Multiple Dual Address Cycle Memory Read Line Memory Read & Invalidate
Bus Command/Byte Enables. During the address phase of a bus transaction, these pins define the bus command (see list above). During the data phase, these pins are byte enables that determine which byte lanes carry meaningful data: byte 0 corresponds to AD0-7, byte 1 to 8-15, byte 2 to 16-23, and byte 3 to 24-31. Initialization Device Select. Used as a chip select during configuration read and write transactions
IOVCC & GND
efmp69030 Databook
Revision 1.3 11/24/99
2-8
Pin Descriptions
B69030 and M69030 Configuration Pins and ROM Interface
BGA Pin D18 C19 B20 C18 A20 B19 A19 B18 C17 D16 B10 C10 A9 B9 A8 C9 B8 A7 C8 B7 A6 C7 B6 A5 C6 D15 B16 A17 C15 A16 B15 C14 A15 B14 C13 A14 B13 D12 C12 A13 B12 L19 L20 mBGA Pin A13 E12 F12 A12 B13 C12 D12 F11 A11 B12 A7 E9 B9 E8 A6 B7 E8 A6 B7 D7 C6 E7 B6 D6 A4 C11 D11 E11 A10 B11 C10 A9 D10 E10 B10 C9 D9 A8 E9 B9 A7 T16 R16 Pin Name CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 RMD0 RMD1 RMD2 RMD3 RMD4 RMD5 RMD6 RMD7 ROMOE# (MCLKOUT) RMA0 RMA1 RMA2 RMA3 RMA4 RMA5 RMA6 RMA7 RMA8 RMA9 RMA10 RMA11 RMA12 RMA13 RMA14 RMA15 RMA16 RMA17 Type Active Powered In In In In In In In In In In In In In In In In IN IN IN IN IN IN IN IN Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a High High High High High High High High Low n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a IOVCC & GND Description CFG0 through CFG15 are latched into registers XR70 and XR71 on reset for use as configuration inputs. Please see register descriptions for XR70 and XR71 for complete details on the configuration options.
IOVCC & GND
RMD0 through RMD7 are used as BIOS ROM data inputs during system startup (i.e., before the system enables the graphics controller memory interface).
IOVCC & GND IOVCC & GND
BIOS ROM Output Enable. May be configured as MCLK output in test mode. These pins are BIOS ROM address outputs RMA0-17. BIOS ROMs are not normally required in portable computer designs (the graphics system BIOS code is normally included in the system BIOS ROM). However, the 69030 graphics accelerator provides BIOS ROM interface capability for development systems and add-in card flat panel graphics controllers. Since the PCI/AGP Bus specifications require only one load on the bus for the entire graphics subsystem, the BIOS ROM interface is "through the chip".
efmp69030 Databook
Revision 1.3 11/24/99
Pin Descriptions
2-9
B69030 and M69030 Flat Panel Display Interface
BGA Pin W6 V7 Y6 W7 V8 Y7 W8 U9 V9 Y8 W9 Y9 V10 W10 Y10 U10 U11 Y11 W11 V11 Y12 Y13 V12 U12 W13 Y14 V13 W14 Y15 V14 W15 Y16 V15 Y17 W16 U15 mBGA Pin R5 N6 P6 T5 M7 R6 N7 T6 P7 L8 R7 M8 T7 N8 R8 K9 T8 R9 T9 P9 M9 K10 L10 R10 M10 P10 N10 T10 M11 R11 T11 P11 M12 N11 R12 P12 Pin Name P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 Type Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Active High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High Powered IOVCC & GND Description Flat panel data bus of up to 36-bits.
efmp69030 Databook
Revision 1.3 11/24/99
2-10
Pin Descriptions
B69030 and M69030 Flat Panel Display Interface (continued)
BGA Pin Y5 W5 Y4 mBGA Pin T4 L7 P5 Pin Name SHFCLK FLM Type Active Powered OUT OUT High High High IOVCC & GND IOVCC & GND IOVCC & GND Description Shift Clock. Pixel clock for flat panel data. First Line Marker. Flat Panel equivalent of VSYNC. Latch Pulse. Flat Panel equivalent of HSYNC. May also be configured as Display Enable (DE) or BLANK#. Some panels use the signal name of CL1. M signal for panel AC drive control (may also be called ACDCLK). May also be configured as BLANK# or as Display Enable (DE) for TFT Panels. Power sequencing control for panel driver electronics voltage VDD. Power sequencing control for panel bias voltage VEE. May also be configured as ENABKL. Power sequencing control for enabling the backlight.
LP (CL1)(DE) (BLANK#) OUT
V6
M6
M (DE) (BLANK#)
OUT
High
IOVCC & GND
V5
N5
ENAVDD
I/O
High
IOVCC & GND
W4
T3
ENAVEE (ENABKL)
I/O
High
U6
R4
ENABKL
I/O
High
Notes: To accommodate a wide variety of panel types, the graphics controller has been designed to output its data in any of a number of formats. These formats include different data widths for the colors belonging to each pixel, and the ability to accommodate different pixel data transfer timing requirements. For STN-DD panels, pins P0 through P35 are organized into groups corresponding to the upper and lower parts of the panel. The names of the signals for the upper and lower parts follow a naming convention of Uxx and Lxx, respectively. For panels that require a pair of adjacent pixels be sent with every shift clock, pins P0 through P35 are organized into groups corresponding to the first and second (from right to left) pixels of each pair of pixels being sent. The names of the signals for the first and second pixels of each such pair follow a naming convention of Fxx and Sxx, respectively. Panels that transfer data on both edges of SHFCLK are also supported. See the description for register FR12 for more details. Signals mapping for 18 bit TFT Panels: B0-B5 should match P2-P7, G0-G5 should match P10-P15, R0-R5 should match P18-P23.
efmp69030 Databook
Revision 1.3 11/24/99
Pin Descriptions
2-11
B69030 and M69030 Flat Panel Display Interface (continued)
Mono SS Pin Name P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 Pixels/ Clock: 8-bit D0 D1 D2 D3 D4 D5 D6 D7 Mono DD 8-bit UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Mono DD 16 bit UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Color TFT 9/12/16 bit B0 B1 B2 B3 B4 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 Color TFT 18/24 bit B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 Color TFT 36-bit FB0 FB1 FB2 FB3 FB4 FB5 SB0 SB1 SB2 SB3 SB4 SB5 FG0 FG1 FG2 FG3 FG4 FG5 SG0 SG1 SG2 SG3 SG4 SG5 FR0 FR1 FR2 FR3 FR4 FR5 SR0 SR1 SR2 SR3 SR4 SR5 SHFCLK 2-2/3 SHFCLK 5-1/3 SHFCLK 2-2/3 SHFCLK 5-1/3 SHFCLK 8 Color TFT-HR 18/24 bit FB0 FB1 FB2 FB3 SB0 SB1 SB2 SB3 FG0 FG1 FG2 FG3 SG0 SG1 SG2 SG3 FR0 FR1 FR2 FR3 SR0 SR1 SR2 SR3 Color STN-SS 8-bit (4bP) R1 B1 G2 R3 B3 G4 R5 B5 Color STN-SS 16-bit (4bP) R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 Color STN-DD 8-bit (4bP) UR1 UG1 UB1 UR2 LR1 LG1 LB1 LR2 Color STN-DD 16-bit (4bP) UR0 UG0 UB0 UR1 LR0 LG0 LB0 LR1 UG1 UB1 UR2 UG2 LG1 LB1 LR2 LG2 Color STN-DD 24-bit UR0 UG0 UB0 LR0 LG0 LB0 UR1 UG1 UB1 LR1 LG1 LB1 UR2 UG2 UB2 LR2 LG2 LB2 UR3 UG3 UB3 LR3 LG3 LB3
SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK 8 8 16 1 1 2 2
See the notes for this table on the previous page.
efmp69030 Databook
Revision 1.3 11/24/99
2-12
Pin Descriptions
B69030 and M69030 CRT Interface
BGA Pin U3 mBGA Pin K7 Pin Name HSYNC (CSYNC) Type Out Active Both Powered IOVCC & GND Description CRT Horizontal Sync (polarity is programmable) or "Composite Sync" for support of various external NTSC/PAL encoder chips. CRT Vertical Sync (polarity is programmable). CRT analog video outputs from the internal color palette DAC. The DAC is designed for a 37.5 equivalent load on each pin (e.g. 75 resistor on the board, in parallel with the 75 CRT load) DACVCC & DACGND IOVCC & GND IOVCC & GND Set point resistor for the internal color palette DAC. A 528 1% resistor is required between RSET and DACGND. General purpose I/O, suitable for use as DDC Data. General purpose I/O, suitable for use as DDC Clock. These two pins are functionally suitable for a DDC interface between the graphics controller chip and a CRT monitor.
V2
R1
VSYNC
Out
Both
IOVCC & GND DACVCC & DACGND
Y3 V4 W3
K6 P4 T2
RED GREEN BLUE
Out Out Out
Analog Analog Analog
W2
T1
RSET
In
N/A
V3
R2
DDC DATA (GPIO2)
I/O
High
U4
N4
DDC CLK (GPIO3)
I/O
High
efmp69030 Databook
Revision 1.3 11/24/99
Pin Descriptions
2-13
B69030 and M69030 Video Interface
BGA Pin V16 W17 Y18 V17 R18 U20 T19 R17 T18 U19 V20 T17 U18 V19 W20 W19 U17 V18 Y19 W18 mBGA Pin T12 M13 R13 N12 N15 T15 P16 M16 N14 P15 M15 L14 R15 T14 P14 N13 R14 M14 T13 L13 Pin Name VREF HREF VCLK PCLK (DCLKOUT) VP0 VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 VP9 VP10 VP11 VP12 VP13 VP14 VP15 Type Active Powered I/O In In Out In In In In In In In In In In In In In In In In High High High High High High High High High High High High High High High High High High High High IOVCC & GND IOVCC & GND IOVCC & GND IOVCC & GND IOVCC & GND Description Vertical Reference Input. Horizontal Reference Input Video Input Clock Video in port PCLK out. May also be configured as the DCLK output in test mode. Video data port data bus. In ZV mode, VP0-7 correspond to Y0-7, and VP8-15 correspond to UV0-7.
efmp69030 Databook
Revision 1.3 11/24/99
2-14
Pin Descriptions
B69030 and M69030 Miscellaneous Pins
BGA Pin E4 mBGA Pin C3 Pin Name STNDBY# Type Active Powered In Low IOVCC & GND Description Standby Control Pin. Pull this pin low to place the chip in Standby Mode. A low-to-high transition on the pin will cause change to exit standby mode, host standby mode, and panel off mode. Reference Clock Input. This pin serves as the input for an external reference oscillator (usually 14.31818MHz). All internal timings are derived from this primary clock input source. Alternatively, this can be configured to be used as an alternate input for an externally provided MCLK through a strapping option and register programming. However, during normal operation, an external MCLK should be provided through the MCLKIN pin. See the descriptions for registers XR70 and XRCF for complete details. Optional input for an externally provided DCLK. Enabled via strapping option and register programming. See the descriptions for registers XR70 and XRCF for complete details. Optional primary input for an externally provided MCLK (the REFCLK(MCKLIN) pin can be used as an alternate input for MCLK). This pin is enabled via strapping option and register programming. See the descriptions for registers XR70 and XRCF for complete details. General Purpose I/O pin #0. Can also be used as the ACTI output (Activity Indicator). General Purpose I/O pin #1. Can also be used as a 32KHz clock input for panel power sequencing. Reserved I/O n/a n/a High n/a n/a IOVCC & GND The default is reserved. May also be configured as the 2nd display's DCLK output in test mode. These two pins are for internal use only and should be left open.
C3
B3
REFCLK (MCLKIN)
In
High
IOVCC & GND
B2
A1
DCLKIN
In
High
IOVCC & GND
B1
E5
MCLKIN
In
High
IOVCC & GND
V1 T4 U16 D6 D17 A12
N3 P2 P13 A5 A14 B8
GPIO0 (ACTI) GPIO1 (32KHz) Reserved Reserved (DCLKOUT2) TMD0 TMD1
I/O I/O
High High
IOVCC & GND IOVCC & GND
efmp69030 Databook
Revision 1.3 11/24/99
Pin Descriptions
2-15
B69030 and M69030 Power and Ground Pins
BGA Pin U5 mBGA Pin Name Pin R3 Description DACVCC should be isolated from all other VCCs, and should not be greater than CORVCC. DACGND should be common with digital ground but must be tightly coupled to DACVCC. MCKVCC and DCKVCC must be at the same voltage level as CORVCC. Each of the MCKVCC/MCKGND and DCKVCC/DCKGND pairs must be INDIVIDUALLY decoupled. Balls D5 and C4 (DCKVCC) may be jumpered together. Balls B4 and A3 (DCKGND) may be jumpered together Refer to the section on clock generation for suggested clock power and ground PCB layout. D7 G4 P4 U14 U7 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 F6 G6 H6 F7 F8 H8 F9 G9 H9 J9 H10 H11 J11 H12 J12 H13 J13 H14 J14 K14 L15 Digital ground. GND DACVCC Analog power for the internal RAMDAC.
Y2
M5
DACGND Analog ground for the internal RAMDAC.
B3 A2
D4 A2
MCKVCC Analog power and ground pins for the MCKGND internal memory clock synthesizer (MCLK).
C4 D5 A3 B4
B4 E6 A3 C5
DCKVCC Analog power and ground pins for the internal dot clock synthesizer (DCLK). DCKGND
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Pin Descriptions
B69030 and M69030 Power and Ground Pins (continued)
D9 W12 D8 J7 C7 P8 J10 D14 E14 F14 G15 H15 J15 P3 CORVCC Digital power for the graphics controller internal logic (a.k.a., the "core" VCC).
D14 G17 P17
MEMGND Embedded memory ground.
M9 M10 M11 M12 Y1 H4 N4 U8 U13 W1
RGND
Internal reference GND, should be tied to GND.
G7 G8 H7 J8 K8 K11 K12 K13 L11 L12 N9 L6 F10 G10 G11 G12 G13 G14 K15 L9
IOVCC
I/O Power.
D13 H17 N17
MEMVCC Power for embedded memory.
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Pin Descriptions
2-17
B69030 and M69030 Reserved and No Connection Pins
BGA PIN A1 B5 C2 C5 D3 D4 D8 Y20 A10 A11 A18 B11 B17 C11 C16 C20 D10 D11 D19 D20 E17 E18 E19 E20 F17 F18 F19 F20 G18 G19 G20 H18 H19 H20 J17 J18 J19 J20 K17 K18 K19 K20 L17 L18 M17 M18 M19 M20 N18 N19 N20 P18 P19 P20 R19 R20 T20 mBGA Pin Name PIN B1 Reserved
C8 C13 D13 E13 F13 B14 C14 A15 B15 C15 D15 E15 F15 A16 B16 C16 D16 E16 F16 G16 H16 J16 K16 L16 N16 B2 C4 D5
No Connection
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Pin Descriptions
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3-1
Chapter 3 Electrical Specifications
Introduction
Chapter 3 describes the Electrical Specifications for the B69030 and M69030 Dual HiQVideo Accelerator. Table 3-1:
Symbol VCC VI TSTG
Absolute Maximum Conditions
Parameter Supply Voltage Input Voltage Storage Temperature Min -0.5 -0.5 -40 Max 5.0 5.5 125 Units V V C
Note:
Permanent device damage may occur if Absolute Maximum Rating are exceeded. Operation must be restricted to the conditions under Normal Operating Conditions.
Table 3-2:
Symbol VCC TA
Normal Operating Conditions
Parameter Supply Voltage Ambient Temperature Min 3.0 0 Typical 3.3 -- Max 3.6 70 Units V C
Table 3-3:
Symbol IO
DAC Characteristics
Parameter Full Scale Output Current Full Scale Error DAC to DAC Correlation DAC Linearity Notes RSET=560 and 37.5 Load Min - - - 2 Typical 18.6 - 1.27 - Max - 5 - - Units mA % % LSB
Note:
These values apply under normal operating conditions unless otherwise noted.
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3-2 Table 3-4:
PD IIL IOZ VIL VIH VOL VOH
Electrical Specifications DC Characteristics.
Notes All VCCs at 3.3V MCLK=83MHz, DCLK=110MHz High Impedance All input pins All input pins Under max load per table 16-5 (3.3V) Under max load per table 16-5 (3.3V) Min - -100 -100 -0.5 0.6xVcc - 0.7xVcc Max 1.0 +100 +100 0.8 5.5 0.5 - Units W A A V V V V Power Dissipation Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Symbol Parameter
Notes: These values apply under normal operating conditions unless otherwise noted. For power configuration data, please refer to an appropriate application note.
Table 3-5:
Symbol IOL
DC Drive Characteristics
Parameter Output Low Current Output Pins H/VSYNC, P0-P35, SHFCLK, M DEVSEL#, PAR, PERR#, SERR#, STOP#, TRDY# 8 ACTI, AD0-AD31, ENABKL, ENAVDD, ENAVEE, FLM, LP All other outputs 2 VOUTVOL and VCC=3.3V 12 mA mA Output High Current H/VSYNC, P0-P35, SHFCLK, M DEVSEL#, PAR, PERR#, SERR#, STOP#, TRDY# 8 ACTI, AD0-AD31, ENABKL, ENAVDD, ENAVEE, FLM, LP All other outputs 2 mA mA mA DC Test Conditions VOUTVOL and VCC=3.3V Min 12 Units mA
IOH
Note:
These values apply under normal operating conditions unless otherwise noted.
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Electrical Specifications Table 3-6:
VCC VTEST VIL VIH TR TF
3-3
AC Test Conditions:
Minimum 3.1 0.4 VCC 0.9 VCC 3 2 Maximum 3.6 1.5 0.1 VCC VCC - 0.1 3 2 Units V V V V ns ns
Symbol Parameter Supply Voltage All AC parameters Input low voltage (10% of VCC) Input high voltage (90% of VCC) Maximum input rise time (3.3/5V) Maximum input fall time (3.3/5V)
Tester Inputs
VTEST
TF
TR VCC VIH
Tester VCC Outputs VIH
VIL 0 0 VIL
Figure 3-1: AC Test Timing
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3-4 Table 3-7:
Symbol FREF TREF THI /TREF
Electrical Specifications AC Timing Characteristics - Reference Clock
Parameter Reference Frequency Reference Clock Period Reference Clock Duty Cycle Notes Min 1 16.6 40 Typical 14.31818 69.84128 - Max 60 1000 60 Units MHz ns %
TREF THI
Reference Clock Input
Figure 3-2: Reference Clock Timing
Table 3-8:
Symbol FDCLK FMCLK
AC Timing Characteristics - Clock Generator
Parameter DCLK Frequency MCLK Frequency Notes Min - - Typical - - Max 170 83 Units MHz MHz
Table 3-9:
TIPR TORS TRES TSTR TRSR TRSO TCSU TCHD
AC Timing Characteristics - Reset
Notes See Note 1 See Note 2 RESET# is ignored in Standby Mode measured 0.1Vcc to 0.9Vcc See Note 3 Min 1 0 1 2 - - 20 5 Max - - - - 20 40 - - Units ms ms ms ms ns ns ns ns
Symbol Parameter Reset Inactive from Power Stable Reset Inactive from Ext. Osc. Stable Minimum Reset Pulse Width Reset Inactive from Standby Inactive Reset Rise Time Reset Active to Output Float Delay Configuration Setup Time Configuration Hold Time
Note 1: This parameter includes time for internal voltage stabilization of all sections of the chip, startup and stabilization of the internal clock synthesizer, and setting of all internal logic to a known state. Note 2: This parameter includes time for the internal clock synthesizer to reset to its default frequency and time to set all internal logic to a known state. It assumes power is stable and the internal clock synthesizer is already operating at some stable frequency. Note 3: This parameter specifies the setup time to latch reliably the state of the configuration bits. Changes in some configuration bits may take longer to stabilize inside the chip (such as internal clock synthesizer-related bits 4 and 5). The recommended configuration bit setup time is TRES to insure that the chip is in a completely stable state when Reset goes inactive.
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Electrical Specifications
3-5
Initial Power-Up Reset
Reset with Chip Operating and Power Stable
VCC 14.318 MHz
TIPR
STABLE
TORS
STNDBY#
TSTR TRES TRSR TCHD TCSU TCHD
RESET#
TRSR
Configuration Inputs CFG0-15
TCSU
TRSO
Bus Output Pins
Table 3-10:
Symbol TFRS TCMS TCMH TBES TBEH TADS TADH TDAS TDAH TDAD TTZH TTHL TTLH TTHZ TDZL TDLH TDHZ TISC TIHC
Figure 3-3: Reset Timing AC Timing Characteristics - PCI Bus Frame (CLK=33MHz)
Notes Min 7 7 0 7 0 7 0 7 0 2 2 2 2 1 2 2 1 7 0 Max - - - - - - - - - 11 11 11 11 - 11 11 - - - Units ns ns ns ns ns ns ns ns ns ns ns ns ns CLK ns ns CLK ns ns
Parameter FRAME# Setup to CLK C/BE#[3:0] (Bus CMD) Setup to CLK C/BE#[3:0] (Bus CMD) Hold from CLK C/BE#[3:0] (Byte Enable) Setup to CLK C/BE#[3:0] (Byte Enable) Hold from CLK AD[31:0] (Address) Setup to CLK AD[31:0] (Address) Hold from CLK AD[31:0] (Data) Setup to CLK AD[31:0] (Data) Hold from CLK AD[31:0] (Data) Valid from CLK TRDY# High Z to High from CLK TRDY# Active from CLK TRDY# Inactive from CLK TRDY# High before High Z DEVSEL# Active from CLK DEVSEL# Inactive from CLK DEVSEL# High before High Z IRDY# Setup to CLK IRDY# Hold from CLK
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Electrical Specifications
CLK FRAME#
Hi-Z
1
TFRS
2
3
4
Bus Hi-Z Turnaround
T CMS
TCMH
C/BE#[3:0]
Hi-Z
TBES Byte Enables
TBEH Byte Enables TDAD Bus Hi-Z Turnaround
Command TADH
TADS
TDAH Read Data Bus Hi-Z Turnaround
Read AD[31:0]
Hi-Z
Address TADS TADH
Read Turnaround
TDAS
TDAH Bus Hi-Z Turnaround T THZ Hi-Z
Write AD[31:0]
Hi-Z
Address TTZH
Write Data T THL
Write Data T TLH
TRDY#
Hi-Z
Bus Turnaround
T ISC
T IHC Hi-Z
IRDY#
Hi-Z
Bus Turnaround
T DZL
TDLH
T DHZ Hi-Z
DEVSEL#
Hi-Z
Bus Turnaround
Table 3-11:
Symbol TSZH TSHL TSLH TSHZ
Figure 3-4: PCI Bus Frame Timing AC Timing Characteristics - PCI Bus Stop (CLK=33MHz)
Notes Min 2 2 2 1 Max 11 11 11 - Units ns ns ns CLK
Parameter STOP# High Z to High from CLK STOP# Active from CLK STOP# Inactive from CLK STOP# High before High Z
CLK STOP#
High Z
TSZH
TSHL
TSLH
TSHZ
Figure 3-5: PCI Bus Stop Timing
Table 3-12:
Symbol TROE TROM
AC Timing Characteristics - PC BIOS ROM
Notes Min - - Max 40 150 Units ns ns
Parameter ROMOE# Active from CLK Slowest Permissible BIOS ROM Access Speed
Note:
PCI BIOS ROM timing is derived from the PCI bus clock. Timing sequences are fixed assuming
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the use of widely-available, low-cost, typical industry-standard EPROMs. Timing specifications and performance of BIOS ROM memory accesses are non-critical since PCI BIOS ROM data is always shadowed into high-speed system memory prior to execution of BIOS code.
7 CLK
7 CLK
7 CLK
7 CLK
CLK FRAME#
AD
ROM Add TROE
Data Valid
ROMOE#
ROMA TRDY#
Byte 0 Add Byte 1 Add Byte 2 Add
Byte 3 Address
Table 3-13:
Symbol TVPS TVPH THRS THRH TVRS TVRH FVCLK
Figure 3-6: PCI BIOS ROM Timing AC Timing Characteristics - Video Data Port
Parameter Notes Min 5 3 5 In ZV-Port Mode 3 5 3 10 40 Max - - - - - - 33 60 Units ns ns ns ns ns ns MHz %
VP0 - VP15 (Incoming Data) Setup VP0 - VP15 (Incoming Data) Hold HREF (Incoming HS) Setup HREF (Incoming HS) Hold VREF (Incoming VS) Setup VREF (Incoming VS) Hold VCLK Frequency (TVCLK is VCLK period) VCLK Duty Cycle
Table 3-14:
Symbol TSCLK TDOVD TCOVD
Figure 3-7: Video Data Port Timing AC Timing Characteristics - Panel Output Timing
Parameter SHFCLK cycle time DE and P[35..0] Output Valid Delay LP and FLM Output Valid Delay SHFCLK Duty Cycle Measured at 0.4VCC Signaling Min 15 -3 -3 40 Max - 4 3 60 Units ns ns ns %
Note:
AC Timing is valid when max output loading=25pF.
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Electrical Specifications
TVCLK
VCLK
TVPS TVPH
VP0 -VP15
THRS THRH
HREF
TVRS
TVRH
VREF
TSLK
SHFCLK
TDOVD
DE, P[23..0]
TCOVD
LP, FLM
Figure 3-8: Panel Output Timing Table 3-15:
Symbol TDAD TTZH TTHL TTLH TTHZ
AC Timing Characteristics - A.G.P. 1x AC Timing Parameters
Parameter Output Timing AD[0] (Data) Valid from CLK TRDY# High Z to High from CLK TRDY# Active from CLK TRDY# Inactive from CLK TRDY High before High Z Min 1ns 1ns 1ns 1ns Max 6ns 6ns 5.5ns 5.5ns 14ns Notes 1 1 1 1
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Electrical Specifications Table 3-15:
TDZL TDLH TDHZ TSZH TSHL TSLH TSHZ TADS TADH
3-9
AC Timing Characteristics - A.G.P. 1x AC Timing Parameters (Continued)
DEVSEL# Active from CLK DEVSEL# Inactive from CLK DEVSEL# High before High Z STOP# High Z to High from CLK STOP# Active from CLK STOP# Inactive from CLK STOP# High before High Z Address/Read/Write Cycle Input Timing Address Setup to CLK Address Hold from CLK 6ns 0ns 1ns 1ns 1ns 1ns 1ns 5.5ns 5.5ns 14ns 6ns 5.5ns 5.5ns 14ns 1 1 1 1 1
Note: 1 - AC Timing is valid when max output loading = 10 pF per the Intel Accelerated Graphics Port Interface Specification Revision 2.0, however, actual test load capacitance may vary from the max output loading of 10 pF.
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Electrical Specifications
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Mechanical Specifications
4-1
Chapter 4 Mechanical Specifications
Introduction
Figure 4-1 and 4-2 illustrates the Mechanical Specifications of the B69030 and M69030 Dual HiQVideo Accelerator respectively.
Top View
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1.435mm (0.0565")
27 =0.1 m (1.063 0.004") m
1.27mm (0.0500") BSC
Diameter: 0.760 0.16 (0.0299 0.0023) 256 +16 places 2.2mm max (0.087")
27 0.1 mm (1.063 0.004") A B C D E F G H J K L M N P R T U VW Y
Bottom View
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1.435mm (0.0565")
27 =0.1 m (1.063 0.004") m
1.27mm (0.0500") BSC
Diameter: 0.760 0.16 (0.0299 0.0023) 256 +16 places 1.53mm (0.0602") max
27 0.1 mm (1.063 0.004")
YWVU T R PNM L K J HG FE DCB A
Figure 4-1: 256+16-Contact Ball Grid Array
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Mechanical Specifications
17.00 +/- .20mm
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D
1.00 +/0.10mm
E F G H
15.0 BSC
J K L M N P R T
17.00 +/- .20mm
1.00 +/0.10mm 15.0 BSC
1.45 +/- .10mm
0.40 +/- .05mm
Figure 4-2: 256 Ball - Mini Ball Grid Array
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I/O and Memory Address Maps
5-1
Chapter 5 I/O and Memory Address Maps
Introduction
An extensive set of registers normally controls the graphics system. These registers are a combination of registers defined by IBM when the Video Graphics Array (VGA) was first introduced, and others that have been added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go well beyond the original VGA standard. This chapter provides an overview of the address locations and sub-indexing mechanisms used to access the various registers and the frame buffer of this graphics controller. Some of the registers are directly accessible at various I/O addresses. They may be read-only or write-only, and some must be read from and written to at different I/O addresses. Most of the other registers are accessed through a sub-indexing arrangement. The index of the desired register is written to an index register, and then the desired register may be read from or written to through a data port. Almost all of these sub-addressed registers are both readable and writable. Still other registers are directly accessible at various memory addresses and here too, almost all of these registers are both readable and writable.
VGA-Compatible Address Map
Part of the VGA standard requires the VGA graphics system to take the place of either the IBM Monochrome Display and Printer Adapter (either MDPA or MDA) or the IBM Color Graphics Adapter (CGA). This was also the case with the IBM Enhanced Graphics Adapter (EGA), VGA's predecessor. The MDA has registers at I/O addresses 3B4-3B5 and 3BA, and a character buffer (not a frame buffer -- the MDA is a text-only device) within the memory address range of B0000-B7FFF. The CGA has registers within I/O addresses 3D4-3D5 and 3DA-3DC, and a frame buffer (for either text or graphics) within the memory address range of B8000-BFFFF. The VGA standard introduced numerous modes with features that went beyond those originally provided by either MDA or CGA. To do this, the VGA standard introduced many additional registers at locations in the 3C0-3CF I/O address range, and an additional frame buffer memory space in the A0000-AFFFF memory address range through which the frame buffer could be accessed. This additional memory address region is a 64KB "port-hole" by which the standard 256KB VGA frame buffer is accessed. Either different 64KB portions of this frame buffer are swapped or "paged" in and out of this port-hole as a way of gaining access to all of it, or this frame buffer can be reorganized into "planes" that can be made selectively or even simultaneously accessible though this port-hole as part of a mechanism to enable bit-wise graphics color manipulation. This was done as part of the VGA standard partly because of the shortage of available addresses in the first 1MB of memory address space in PC-standard systems. If a PC with a VGA graphics system does not have either an MDA display system or a CGA graphics system, the VGA BIOS will initialize the VGA graphics system to take the place of either an MDA if a monochrome display is attached to the VGA, or of a CGA if a color display is attached. However, if a PC with a VGA graphics system also has an MDA display system, the VGA is initialized to take the place of a CGA, regardless of the type of monitor attached to the VGA in order to avoid conflicts with the MDA. Likewise, if a PC with a VGA graphics system also has a CGA graphics system, the VGA is initialized to take the place of an MDA, regardless of the type of monitor attached to the VGA. The VGA standard does not allow a system to have both an MDA display system and a CGA graphics system in the same PC along with a VGA graphics system.
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I/O and Memory Address Maps
Address Maps for Going Beyond VGA
This graphics controller improves upon VGA by providing additional features that are used through numerous additional registers. Many of these additional registers are simply added to the sub-indexing schemes already defined in the VGA standard, while others are added through sub-indexing schemes using additional I/O address locations 3D0-3D3 and 3D6-3D7. This graphics controller also provides for the memory-mapping of both the standard VGA and these additional registers alongside I/O-mapping. All of the registers that are accessible via I/O addresses 3B0 through 3DF are also accessible at offsets 400760 through 4007BF from the starting address of the upper memory space. Still more of these additional registers are 32 bits wide and for performance reasons are accessible exclusively at other offsets from the starting address of the upper memory space. This graphics controller also supports 1 or more megabytes of frame buffer memory -- far larger than VGA's standard complement of 256KB. As an improvement upon the VGA standard frame buffer port-hole, this graphics controller also maps the entire frame buffer into part of a single contiguous memory space at a programmable location, providing what is called "linear" access to the frame buffer. The size of this memory space is 16MB (however, the frame buffer does not fill this entire memory space), and the base address is set through a PCI configuration register. Most aspects of the host interface of this graphics controller are configured through a set of built-in PCIcompliant setup registers. The system logic accesses these registers through standard PCI configuration read and write cycles. Therefore, the exact location of the PCI configuration registers for this graphics controller, as well as any other PCI device in the system I/O or memory address space depends on the system logic design and the system software that configures the system.
Lower Memory Map
Table 5-1:
Address Range A0000-AFFFF B0000-B7FFF B8000-BFFFF C0000 up to CFFFF
Lower Memory Map
Function VGA Frame Buffer MDA Emulation Character Buffer CGA Emulation Frame Buffer VGA BIOS ROM Size in Bytes 64KB 32KB 32KB up to 64KB
I/O and Sub-Addressed Register Map
Table 5-2:
I/O Address 3B0-3B3 3B4 3B5 3B6-3B9 3BA 3BB-3BF 3C0 400780 & C00780 Attribute Controller Index Attribute Controller Index and Data Port 400774 & C00774 Input Status Register 1 (ST01) (MDA Emulation) Feature Control Register (FCR) (MDA Emulation) 400768 & C00768 400769 & C00769 CRTC Index (MDA Emulation) CRTC Data Port (MDA Emulation)
I/O and Sub-Addressed Register Map
Memory Offset Read Write
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I/O and Memory Address Maps Table 5-2:
3C1 3C2 3C3 3C4 3C5 3C6 3C7 3C8 3C9 3CA 3CB 3CC 3CD 3CE 3CF 3D0 3D1 3D2 3D3 3D4 3D5 3D6 3D7 3D8-3D9 3DA 3DB-3DF 4007B4 & C007B4 Input Status Register 1 (ST01) (CGA Emulation) Feature Control Register (FCR) (CGA Emulation) 400788 & C00788 400789 & C00789 40078C & C0078C 40078D & C0078D 400790 & C00790 400791 & C00791 400794 & C00794 400795 & C00795 400798 & C00798 400799 & C00799 40079C & C0079C 40079D & C0079D 4007A0 & C007A0 4007A1 & C007A1 4007A4 & C007A4 4007A5 & C007A5 4007A8 & C007A8 4007A9 & C007A9 4007AC & C007AC 4007AD & C007AD Color Palette State Sequencer Index Sequencer Data Port Color Palette Mask Color Palette Read Mode Index Color Palette Write Mode Index Color Palette Data Port Feature Control Register (FCR) Memory Space Shadowing Register (MSS) Misc. Output Register (MSR) I/O Space Shadowing Register (IOSS) Graphics Controller Index Graphics Controller Data Port Flat Panel Extensions Index Flat Panel Extensions Data Port Multimedia Extensions Index Multimedia Extensions Data Port CRTC Index (CGA Emulation) CRTC Data Port (CGA Emulation) Configuration Extensions Index Configuration Extensions Data Port
5-3
I/O and Sub-Addressed Register Map (Continued)
400781 & C00781 400784 & C00784 Attribute Controller Data Port Input Status Register 0 (ST00) Alternate Attribute Controller Data Port Misc. Output Register (MSR)
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I/O and Memory Address Maps
Sub-Indexing Indices and Data Ports
Table 5-3:
Index Port Addresses
Sub-Indexing Indices and Data Ports
Data Port Addresses Register Group Name CR00-2F CR30-3F CR40-4F CR50-5F CR60-6F CR70-7F CR80-FF SR0-7 GR0-8 AR0-14 XR00-0F XR10-1F XR20-2F XR30-3F XR40-4F XR50-5F XR60-6F XR70-7F XR80-8F XR90-9F XRA0-AF XRB0-BF XRC0-CF XRD0-DF XRE0-EF XRF0-FF FR00-06 FR07-1F FR20-2F FR30-3F FR40-47 FR48-4F FR50-5F FR60-6F FR70-7F MR00-01 MR02-18 MR1E-3F MR40-42 MR43-44 MR45-9D MR9E-BF MRC0-C2 MRC3-C4 MRC5-FF Function Basic Display Control Timing Extension Bits Address Extension Bits Display Overlay -- Interlace Control -- VGA Sequencer Control VGA Data Path Control VGA Attributes Control General Configuration -- Graphics Engine Configuration -- Memory Configuration -- Pin Control Configuration Pins Pixel Pipeline Software Flags Hardware Cursor -- Clock Control Power Management Software Flags Hardware Testing Pipeline Control General Panel Control Horizontal Panel Timing Vertical Panel Timing Horizontal Compensation Vertical Compensation -- -- -- Capability Flags Acquisition/Capture Playback Engine Color Key Display Line Count -- Playback Engine Color Key Display Line Count --
I/O 3B4/3D4 Mem 0x400768/7A8
I/O 3B5/3D5 Mem 0x400769/7A9
CRTC
I/O 3C4 Mem 0x400788 I/O 3CE Mem 0x40079C I/O 3C0 Mem 0x400780
I/O 3C5 Mem 0x400789 I/O 3CF Mem 0x40079D I/O 3C0/3C1 Mem 0x400780/781
Sequencer Graphics Controller Attribute Controller
I/O 3D6 Mem 0x4007AC
I/O 3D7 Mem 0x4007AD
Extension Registers
I/O 3D0 Mem 0x4007A0
I/O 3D1 Mem 0x4007A1
Flat Panel
I/O 3D2 Mem 0x4007A4
I/O 3D3 Mem 0x4007A5
Multimedia
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I/O and Memory Address Maps
5-5
Register Shadowing Schemes for Dual-Pipe
To answer the need to create two pixel pipelines that are both compatible with the VGA standard, a scheme involving a combination of "sharing" and "shadowing" of registers accessed via the I/O space is used. To accommodate different operating system driver architectures, another scheme of sharing and shadowing is employed for registers accessed via the memory space. Shared registers are generally used to support hardware that is shared by both pipelines, or that is meant to be reassignable from one pipeline to the other. Shared registers are designed to be accessible to the driver code controlling either pipe whether they are accessed via the I/O or memory-mapped register space shadowing schemes. Shadowed registers are generally used to support hardware that belongs exclusively to one pipeline or the other. Each of the two shadows of a register are usually meant to be bit-for-bit identical to the other, and to perform the same functions, but for different pipelines. Shadowed registers are generally intended to be accessible only to the driver code controlling the functions of the pipeline to which that driver belongs, even though the hardware controlling the shadowing schemes used in both I/O and memory-mapped register spaces can be configured to allow the shadowed registers of both pipelines to be write-accessible at the same time by a driver belonging to only one of the pipelines. The I/O and memory-mapped register space shadowing schemes, do not apply to the PCI configuration registers, which are accessible only via the PCI configuration space. Also, there is only one frame buffer, and it is not put through any form of shadowing scheme.
I/O Space Register Shadowing
To ensure VGA compatibility for both pipelines, a "shadowing" scheme is used to allow the I/O-accessible registers of both pipelines to be accessible by the host CPU at the usual I/O address locations. In essence, the registers for each pipeline will be "swapped" into and out of the usual I/O locations, so that existing software can be made to unknowingly program one and/or the other pipeline's registers at any given time. This I/O space shadowing scheme is controlled through the I/O Space Shadowing Register (IOSS) located at I/O address 3CDh. Through this register it is possible to select one or the other of the pipelines' I/Oaddressable registers to be accessible for reading, and it is possible to enable one or the other, or both, or neither of the pipelines' I/O-addressable registers to be accessible for writing.
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5-6 Table 5-4:
I/O and Memory Address Maps I/O Space Register Shadowing Shared
IOSS MSS FCR bits 7-6 and 3-2 of MSR bit 7 of ST00 ST01 CR00 to CR70 no equivalent here SR00 SR01 SR02 to SR07 GR00 to GR05 bit 0 of GR06 AR00 to AR14 DACMASK DACSTATE DACRX DACWX DACDATA XR00 to XR08 XR09 XR0A to XR3F XR40 XR41 to XR7F XR80 to XR82 XR83 to XR9F XRA0 to XRA7 XRA8 to XRC7 XRC8 to XRCB XRCC to XRCF bits 4 and 2-1 of XRD0 XRE0 to XRE3 XRE4 to XRFF FR00-FR01 FR02-FR06 FR07 onward MR00-MR18 bits 7-6 and 4-0 of MR1E (playback engine 1) MR1F-MR42 (playback engine 1) bit 5 of MR1E no equivalent here FR00-FR01 bits 7-6 and 4-0 of MR1E (playback engine 1) MR1F-MR42 (playback engine 2) FR00-FR01 bits 7-5, 3 and 0 of XRD0 XRD1 to XRDF XRE0 to XRE3 bits 4 and 2-1 of XRD0 XRC8 to XRCB XRA0 to XRA7 XR80 to XR82 XR40 XR09 bits 7-1 of GR06 GR07 to GR08 AR00 to AR14 DACMASK DACSTATE DACRX DACWX DACDATA bit 0 of GR06 SR01 bits 5-4 and 1-0 of MSR bits 6-0 of ST00 FCR bits 7-6 and 3-2 of MSR bit 7 of ST00 ST01 CR00 to CR70 CR71 onward
Shadowed for Pipeline A
Shadowed for Pipeline B
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I/O and Memory Address Maps Table 5-4: I/O Space Register Shadowing (Continued)
MR43-MR44 bits 7-6 and 4-0 of MR9E (playback engine 2) MR9F-MRC2 (playback engine 2) BR00 to BR0F ER00 to ER0F bit 5 of MR9E MR43-MR44 bits 7-6 and 4-0 of MR9E (playback engine 1) MR9F-MRC2 (playback engine 1)
5-7
Memory Space Register Shadowing
When the graphics controller is used in dual-pipe mosaic mode with newer operating systems, it is expected that each pipeline will be controlled by its own incarnation of a 2D driver, and that each driver will need to be given its own memory address range through which it controls the registers belonging to its pipeline. To accommodate this, a memory-map address mode is provided wherein one pipeline has its registers mapped within memory offsets 400000 through 7FFFFF while the registers of the other pipeline are mapped to memory offsets C00000 through FFFFFF. The essential idea is to allow each incarnation of the 2D driver to control the pipeline corresponding to it, while staying out of the way of the other incarnation. However, when the graphics controller is used in dual-pipe simultaneous mode, it is generally expected that only one incarnation of the 2D driver will be loaded, and that it will be the same driver that is normally used to control all single-pipeline modes. Such a driver may not be written to make duplicate reads and writes to two pipelines in order to get the same thing going on both, and so, as in the case of the I/O space, a "shadowing" scheme is implemented in the memory space, such that the one 2D driver may write to the same registers in both pipelines simultaneously in single write operations. This shadowing scheme is under the control of the Memory Space Shadowing Register (MSS). MSS provides a means of temporarily choosing one or the other of the two sets of registers to be made writable for those few occasional situations where a register belonging to one pipeline must be set to something different from the same register belonging to the other pipeline. MSS also provides the mechanism by which one or the other of the two sets of registers is selected for read operations, since it is not possible to read from both sets simultaneously.
Video Playback Engine Register Cross-Sharing
This graphics controller has two video playback engines, numbers 1 and 2, to answer both the need to show the same playback image through both pipes in dual-pipe simultaneous mode, and the need to show two different images for video conferences in either dual-pipe mosaic mode or the single-pipe modes. To do all of these things, the two video playback engines are "reassignable" -- i.e., each playback engine can be set to be used with either pipe. Through I/O space shadowing, parallel sets of MR register locations, specifically MR1E through MR42, are created for each pipeline which permit one playback engine to be used with each pipe. However, to use both playback engines simultaneously with either one or the other of the two pipes, a second set of shadowed MR register locations (MR9E through MRC2) has been allocated to allow access to a second playback engine. The following figure shows this interplay of registers and register locations with three of the main elements of the multimedia portion of the graphics controller: a video data capture engine and two video playback engines.
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5-8
I/O and Memory Address Maps
MR02 to MR1A Video Data Capture Registers
Same Registers
Video Data Capture Engine
Video Playback Engine 1
MR1E to MR42 Pipeline A Pri. Playback Registers
MR1E to MR42 Pipeline B Pri. Playback Registers
Video Playback Engine 2
MR9E to MRC2 Pipeline A Sec. Playback Registers Pipeline A MR Register Shadow
MR9E to MRC2 Pipeline B Sec. Playback Registers Pipeline B MR Register Shadow
As shown, there is one set of registers for the video data capture engine, and this set is shared between both pipelines at register locations MR02-MR1A -- i.e., this one set of registers is accessible at register locations MR02-MR1A in both shadows of the MR register set. Where the playback engines are concerned, technically speaking, the registers for each of them are shared between the two pipes, but they are not shared at the same register locations across both pipelines -- they are "cross-shared" as mentioned earlier to allow both video playback engines to be accessible through the shadow belonging to either pipe. The registers of video playback engine 1 are accessible at MR1E-MR42 of pipeline A's shadow of the MR register set and at MR9E-MRC2 of pipeline B's shadow. Taking the reverse of video playback engine 1, the registers of video playback engine 2 are accessible at MR9E-MRC2 of pipeline A's shadow, and at MR1E-MR42 of pipeline B's shadow. In either dual-pipe simultaneous mode or dual-pipe mosaic mode where each pipe is making use of a video playback engine, it is presumed that pipeline A would be using playback engine 1 through its shadow of register locations MR1E-MR42, while pipeline B would be using playback engine 2 through its shadow of the same register locations. In dual-pipe mosaic mode or the single-pipe modes where one pipe, pipeline A for example, were making use of both video playback engines, playback engine 1 would be used through pipeline A's shadow of register locations MR1E-MR42, and playback engine 2 would be used through pipeline A's shadow of register locations MR9E-MRC2.
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I/O and Memory Address Maps
5-9
Two-Way Sub-Indexed Register Indices
Using the previously described I/O and memory space shadowing schemes, it is possible to access the 8bit registers (IOSS, MSS, FCR, MSR, ST00, ST01, ARxx, CRxx, FRxx, GRxx, MRxx, XRxx, and DAC registers) in three ways -- i.e., via the I/O register space and via both the pipeline A and pipeline B portions of the memory-mapped register space. To prevent conflicts between incarnations of driver code, as well as other software, separate sets of indices, one for pipeline A and the other for pipeline B, are used in accessing the 8-bit sub-indexed registers (i.e., ARxx, CRxx, FRxx, GRxx, MRxx and XRxx). With the upper memory map set to the appropriate mode, pipeline A has its own dedicated range of addresses (offsets 400000 through 7FFFFFh) in the memory-mapped register space, and all accesses made to the sub-indexed registers through that memory space make use of set A of the sub-indexed register indices. Likewise, pipeline B also has its own dedicated range of addresses (offsets C00000h to FFFFFFh) in the memory-mapped register space, and all accesses made to the sub-indexed registers through it make use of set B of the sub-indexed register indices. This tying of the use of one or the other set of sub-indexed register indices to the choice of memory space used in making a given access is maintained, regardless of how the MSS register is set. Accesses made to the sub-indexed registers via the I/O space can be made to use one or the other of either set A or set B of the sub-indexed register indices. The IOSS register provides the means of selecting one or both of these sets of indices to be used as appropriate in such accesses.
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5-10
I/O and Memory Address Maps
Upper Memory Map -- Dual-Pipe Mapping
Table 5-5: Upper Memory Map -- Dual-Pipe Mapping
Size 4MB 64 Bytes 1472 Bytes 8MB Pipeline A 4MB 62KB 64KB 3968KB 4MB 64 Bytes 1472 Bytes 8MB Pipeline B 4MB 62KB 64KB 3968KB 64KB 2KB 128 Bytes 128 Bytes 256 Bytes 64KB 2KB 128 Bytes 128 Bytes 256 Bytes Memory Offset 0 to 3FFFFF 400000 to 40003F 400040 to 4005FF 400600 to 40067F 400680 to 4006FF 400700 to 4007FF 400800 to 40FFFF 410000 to 41FFFF 420000 to 7FFFFF 800000 to BFFFFF C00000 to C0003F C00040 to C005FF C00600 to C0067F C00680 to C006FF C00700 to C007FF C00800 to C0FFFF C10000 to C1FFFF C20000 to FFFFFF BitBLT Data Port Pipeline B VGA & Sub-Indexed Registers ER Registers Linear Frame Buffer BitBLT Registers BitBLT Data Port Pipeline A VGA & Sub-Indexed Registers ER Registers Function Linear Frame Buffer BitBLT Registers
Upper Memory Map -- Multiple-Endian Mapping
Table 5-6: Upper Memory Map -- Multiple-Endian Mapping
Size 4MB 64 Bytes 1472 Bytes 8MB Little Endian 62KB 64KB 3968KB 8MB Variable Byte-Swap 4MB 4MB 64KB 64KB 3968KB 4MB 64KB 2KB 128 Bytes 128 Bytes 256 Bytes Memory Offset 0 to 3FFFFF 400000 to 40003F 400040 to 4005FF 400600 to 40067F 400680 to 4006FF 400700 to 4007FF 400800 to 40FFFF 410000 to 41FFFF 420000 to 7FFFFF 800000 to BFFFFF C00000 to C0FFFF C10000 to C1FFFF C20000 to FFFFFF BitBLT Data Port Linear Frame Buffer BitBLT Data Port Pipeline A VGA & Sub-Indexed Registers ER Registers Function Linear Frame Buffer BitBLT Registers
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Register Summaries
6-1
Chapter 6 Register Summaries
Introduction
The Tables in Chapter 6 contain Register Summaries for the 69030 Dual HiQVideo Accelerator. Table 6-1: PCI Configuration Registers
Name VENDID DEVID DEVCTL DEVSTAT REV PRG SUB BASE Register Function Vendor ID Register Device ID Register Device Control Register Device Status Register Revision ID Register Programming Interface Register Sub-Class Code Register Base Class Code Register Reserved (Cache Line Size) Reserved (Latency Timer) Reserved (Header Type) Reserved (Built-In-Self-Test) MBASE Memory Base Address Register Reserved (Base Address) Reserved (Base Address) Reserved (Base Address) Reserved (Base Address) Reserved (Base Address) Reserved SUBVENDID SUBDEVID RBASE Subsystem Vendor ID Register Subsystem Device ID Register ROM Base Address Register Reserved Reserved INTLINE INTPIN Interrupt Line Register Interrupt Pin Register Reserved (Minimum Grant) Reserved (Maximum Latency) SUBVENDSET SUBDEVSET Subsystem Vendor ID Set Register Subsystem Device ID Set Register Access read-only read-only read/clear read-only read-only read-only read-only read-only -- -- -- -- read/write -- -- -- -- -- -- read-only read-only read/write -- -- read/write read-only -- -- read/write read/write Bits 16 16 16 16 8 8 8 8 8 8 8 8 32 32 32 32 32 32 32 16 16 32 32 32 8 8 8 8 16 16
Configuration Space Offset 00 02 04 06 08 09 0A 0B 0C 0D 0E 0F 10 14 18 1C 20 24 28 2C 2E 30 34 38 3C 3D 3E 3F 40 to 6B 6C 6E 6F to FF
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6-2 Table 6-2:
Name IOSS MSS ST00 ST01 FCR MSR
Register Summaries General Control & Status Registers
Register Function I/O Space Shadowing Register Memory Space Shadowing Register VGA Input Status Register 0 VGA Input Status Register 1 VGA Feature Control Register VGA Miscellaneous Output Register Read 3CD 3CB 3C2 3BA/3DA 3CA 3CC Write 3CD 3CB -- -- 3BA/3DA 3C2
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Register Summaries Table 6-3:
Name CR00 CR01 CR02 CR03 CR04 CR05 CR06 CR07 CR08 CR09 CR0A CR0B CR0C CR0D CR0E CR0F CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR22 CR30 CR31 CR32 CR33 CR38 CR3C CR40 CR41 CR70 CR71 CR72 CR73 CR74 CR75 CR76 CR77 CR78 CR79
6-3
CRT Controller Registers
Register Function Horizontal Total Register Horizontal Display Enable End Register Horizontal Blanking Start Register Horizontal Blanking End Register Horizontal Sync Start Register Horizontal Sync End Register Vertical Total Register Overflow Register Preset Row Scan Register Maximum Scanline Register Text Cursor Start Scanline Register Text Cursor End Scanline Register Start Address High Register Start Address Low Register Text Cursor Location High Register Text Cursor Location Low Register Vertical Sync Start Register Vertical Sync End Register Vertical Display Enable End Register Offset Register Underline Row Register Vertical Blanking Start Register Vertical Blanking End Register CRT Mode Control Register Line Compare Register Memory Read Latch Data Register Extended Vertical Total Register Extended Vertical Display End Register Extended Vertical Sync Start Register Extended Vertical Blanking Start Register Extended Horizontal Total Register Extended Horizontal Blanking End Register Extended Start Address Register Extended Offset Register Interlace Control Register NTSC/PAL Video Output Control Register NTSC/PAL Horizontal Serration 1 Start Register NTSC/PAL Horizontal Serration 2 Start Register NTSC/PAL Horizontal Pulse Width Register NTSC/PAL Filtering Burst Read Length Register NTSC/PAL Filtering Burst Read Quantity Register NTSC/PAL Filtering Control Register NTSC/PAL Vertical Reduction Register NTSC/PAL Pixel Resolution Fine Adjust Register Access 3B5/3D5 read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Index Value 3B4/3D4 (CRX) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 22h 30h 31h 32h 33h 38h 3Ch 40h 41h 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h
Note:
CR00-CR22 are standard VGA registers -- all other CR registers are Intel extensions.
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6-4 Table 6-4:
Name SR00 SR01 SR02 SR03 SR04 SR07
Register Summaries Sequencer Register
Register Function Reset Register Clocking Mode Register Map Mask Register Character Map Select Register Memory Mode Register Horizontal Character Counter Reset Register Access (via 3C5) read/write read/write read/write read/write read/write read/write Index Value In 3C4 (SRX) 00 01 02 03 04 07
Table 6-5:
Name GR00 GR01 GR02 GR03 GR04 GR05 GR06 GR07 GR08
Graphics Controller Registers
Register Function Set/Reset Register Enable Set/Reset Register Color Compare Register Data Rotate Register Read Map Select Register Graphics Mode Register Miscellaneous Register Color Don't Care Register Bit Mask Register Access (via 3CF) read/write read/write read/write read/write read/write read/write read/write read/write read/write Index Value In 3CE (GRX) 00h 01h 02h 03h 04h 05h 06h 07h 08h
Table 6-6:
Name
Attribute Controller Register
Register Function Color Data Registers Mode Control Register Overscan Color Register Memory Plane Enable Register Horizontal Pixel Panning Register Color Select Register Access (via 3C0/3C1) read/write read/write read/write read/write read/write read/write Index Value In 3C0 (ARX) 00-0F 10 11 12 13 14
AR00-AR0F AR10 AR11 AR12 AR13 AR14
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Register Summaries Table 6-7: Palette Registers
Register Function Palette Mask Register Palette State Register Palette Read Index Register Palette Write Index Register Palette Data Register Access (via 3C9) read/write read-only write-only read/write read/write I/O Address In 3C7/3C8 3C6h 3C7h 3C7h 3C8h 3C9h
6-5
Name PALMASK PALSTATE PALRX PALWX PALDATA
Table 6-8:
Name XR00 XR01 XR02 XR03 XR04 XR05 XR06 XR08 XR09 XR0A XR0B XR0E XR20 XR40
Extension Register
Register Function Vendor ID Low Register Vendor ID High Register Device ID Low Register Device ID High Register Revision ID Register Linear Base Address Low Register Linear Base Address High Register Host Bus Configuration Register I/O Control Register Frame Buffer Mapping Register PCI Burst Write Support Register Frame Buffer Page Select Register BitBLT Configuration Register Memory Access Control Register Memory Configuration Registers Video Pin Control Register DPMS Sync Control Register GPIO Pin Control Register GPIO Pin Data Register Pin Tri-State Control Register Configuration Pins 0 Register Configuration Pins 1 Register Pixel Pipeline Configuration 0 Register Pixel Pipeline Configuration 1 Register Pixel Pipeline Configuration 2 Register Software Flag Registers Cursor 1 Control Register Cursor 1 Vertical Extension Register Cursor 1 Base Address Low Register Cursor 1 Base Address High Register Cursor 1 X-Position Low Register Cursor 1 X-Position High Register Access (via 3D7) read-only read-only read-only read-only read-only read-only read-only read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Index Value In 3D6 (XRX) 00h 01h 02h 03h 04h 05h 06h 08h 09h 0Ah 0Bh 0Eh 20h 40h 41h-4Fh 60h 61h 62h 63h 67h 70h 71h 80h 81h 82h 90-95 A0h A1h A2h A3h A4h A5h
XR41-XR4F XR60 XR61 XR62 XR63 XR67 XR70 XR71 XR80 XR81 XR82 XR90-XR95 XRA0 XRA1 XRA2 XRA3 XRA4 XRA5
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6-6 Table 6-8:
XRA6 XRA7 XRA8 XRA9 XRAA XRAB XRAC XRAD XRAE XRAF XRC0 XRC1 XRC2 XRC3 XRC4 XRC5 XRC6 XRC7 XRC8 XRC9 XRCA XRCB XRCC XRCD XRCE XRCF XRD0 XRD1 XRD2 XRE0-XREF XRF8-XRFC
Register Summaries Extension Register (Continued)
Cursor 1 Y-Position Low Register Cursor 1 Y-Position High Register Cursor 2 Control Register Cursor 2 Vertical Extension Register Cursor 2 Base Address Low Register Cursor 2 Base Address High Register Cursor 2 X-Position Low Register Cursor 2 X-Position High Register Cursor 2 Y-Position Low Register Cursor 2 Y-Position High Register Dot Clock 0 VCO M-Divisor Low Register Dot Clock 0 VCO N-Divisor Low Register Dot Clock 0 VCO M/N-Divisor High Register Dot Clock 0 Divisor Select Register Dot Clock 1 VCO M-Divisor Low Register Dot Clock 1 VCO N-Divisor Low Register Dot Clock 1 VCO M/N-Divisor High Register Dot Clock 1 Divisor Select Register Dot Clock 2 VCO M-Divisor Low Register Dot Clock 2 VCO N-Divisor Low Register Dot Clock 2 VCO M/N-Divisor High Register Dot Clock 2 Divisor Select Register Memory Clock VCO M-Divisor Register Memory Clock VCO N-Divisor Register Memory Clock VCO Divisor Select Register Clock Configuration Register Powerdown Control Register Power Conservation Control Register 2KHz Down Counter Register Software Flag Registers Test Registers read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read/write read/write A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h E0h-EFh F8h-FCh
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Register Summaries Table 6-9:
Name FR00 FR01 FR02 FR03 FR04 FR05 FR06 FR08 FR0A FR0B FR0C FR0F FR10 FR11 FR12 FR13 FR16 FR17 FR18 FR19 FR1A FR1E FR1F FR20 FR21 FR22 FR23 FR24 FR25 FR26 FR27 FR30 FR31 FR32 FR33 FR34 FR35 FR36 FR37 FR40 FR41 FR48 FR49-4C FR4D FR4E FR70 FR71 FR72 FR73 FR74
6-7
Flat Panel Registers
Register Function Pipeline Feature Register PIpeline Enable & Timing Select Register Output Enable & Assignment Register Output Blanking Register Panel Power Sequencing Delay Register Miscellaneous Control Register Output Disable State Register FP Pin Polarity Register Programmable Output Drive Register FP Pin Control 1 Register Pin Control 2 Register Activity Timer Control Register FP Format 0 Register FP Format 1 Register FP Format 2 Register FP Format 3 Register FRC Option Select Register Polynomial FRC Control Register FP Text Mode Control Register Blink Rate Control Register STN-DD Buffering Control Register M (ACDCLK) Control Register Diagnostic Register FP Horizontal Panel Display Size LSB Register FP Horizontal Sync Start LSB Register FP Horizontal Sync End Register FP Horizontal Total LSB Register FP HSync (LP) Delay LSB Register FP Horizontal Overflow 1 Register FP Horizontal Overflow 2 Register FP HSync (LP) Width and Disable Register FP Vertical Panel Size LSB Register FP Vertical Sync Start LSB Register FP Vertical Sync End Register FP Vertical Total LSB Register FP VSync (FLM) Delay LSB Register FP Vertical Overflow 1 Register FP Vertical Overflow 2 Register FP VSync (FLM) Disable Register Horizontal Compensation Register Horizontal Stretching Register Vertical Compensation Register Text Mode Vertical Stretching 0 MSB Registers Vertical Line Replication Register Selective Vertical Stretching Disable Register TMED Red Seed Register TMED Green Seed Register TMED Blue Seed Register TMED Control Register TMED2 Shift Control Register Access Via Port 3D1h read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Index Value Port 3D0h 00h 01h 02h 03h 04h 05h 06h 08h 0Ah 0Bh 0Ch 0Fh 10h 11h 12h 13h 16h 17h 18h 19h 1Ah 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 30h 31h 32h 33h 34h 35h 36h 37h 40h 41h 48h 49h-4Ch 4Dh 4Eh 70h 71h 72h 73h 74h
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6-8 Table 6-10:
Name MR00 MR01 MR02 MR03 MR04 MR05 MR06-08 MR09-0B MR0C MR0E MR0F MR10 MR11 MR12 MR13 MR14 MR15 MR16 MR17 MR18 MR1E MR1F MR20 MR21 MR22-24 MR25-27 MR28 MR2A MR2B MR2C MR2D MR2E MR2F MR30 MR31 MR32 MR33 MR34 MR3C MR3D-3F MR40-42 MR43 MR44
Register Summaries Multimedia Registers
Register Function Module Capability Register Secondary Capability Register Capture Control 1 Register Capture Control 2 Register Capture Control 3 Register Capture Control 4 Register Capture Memory Address PTR1 Register Capture Memory Address PTR2 Register Capture Memory Width (Span) Register Capture Window X-LEFT Low Register Capture Window X-LEFT High Register Capture Window X-RIGHT Low Register Capture Window X-RIGHT High Register Capture Window Y-TOP Low Register Capture Window Y-TOP High Register Capture Window Y-BOTTOM Low Register Capture Window Y-BOTTOM High Register H-SCALE Register V-SCALE Register Capture Frame Count Register Playback Control 1 Register Playback Control 2 Register Playback Control 3 Register Double Buffer Status & Control Register Playback Memory Address PTR1 Register Playback Memory Address PTR2 Register Playback Memory Line Fetch Width Register Playback Window X-LEFT Low Register Playback Window X-LEFT High Register Playback Window X-RIGHT Low Register Playback Window X-RIGHT High Register Playback Window Y-TOP Low Register Playback Window Y-TOP High Register Playback Window Y-BOTTOM Low Register Playback Window Y-BOTTOM High Register H-ZOOM Register V-ZOOM Register Memory Line Out Total Register Color Key Control 1 Register Color Keys Register Color Key Masks Register Line Count Low Register Line Count High Register Access Via 3D3h read-only read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read-only Index at 3D2h Set to Value 00h 01h 02h 03h 04h 05h 06h - 08h 09h - 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 1Eh 1Fh 20h 21h 22h - 24h 25h - 27h 28h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 3Ch 3Dh - 3Fh 40h - 42h 43h 44h
efmp69030 Databook
Revision 1.3 11/24/99
Register Summaries Table 6-11:
Name BR00 BR01 BR02 BR03 BR04 BR05 BR06 BR07 BR08 BR09 BR0A
6-9
BitBLT Registers
Function Source and Destination Offset Register Pattern/Source Expansion Background Color Register Pattern/Source Expansion Foreground Color Register Monochrome Source Control Register BitBLT Control Register Pattern Address Register Source Address Register Destination Address Register Destination Width & Height Register Source Expansion Background Color Register Source Expansion Foreground Color Register Access read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Offset 0x400000 0x400004 0x400008 0x40000C 0x400010 0x400014 0x400018 0x40001C 0x400020 0x400024 0x400028
Table 6-12:
Name ER00 ER01 ER03
Memory-mapped Wide Extension Registers
Function Central Interrupt Control Register Central Interrupt Status Register Miscellaneous Function Register Access read/write read/write read/write Offset 0x400600 & 0xC00600 0x400604 & 0xC00604 0x40060C & 0xC0060C
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6-10
Register Summaries
This page is intentionally left Blank.
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PCI Configuration Registers
7-1
Chapter 7 PCI Configuration Registers
Introduction
The Tables in Chapter 7 contain the PCI Configuration Registers for the 69030 Dual HiQVideo Accelerator. Table 7-1: PCI Configuration Registers
Name VENDID DEVID DEVCTL DEVSTAT REV PRG SUB BASE Function Vendor ID Register Device ID Register Device Control Register Device Status Register Revision ID Register Programming Interface Register Sub-Class Code Register Base Class Code Register Reserved (Cache Line Size) Reserved (Latency Timer) Reserved (Header Type) Reserved (Built-In-Self-Test) MBASE Memory Base Address Register Reserved (Base Address) Reserved (Base Address) Reserved (Base Address) Reserved (Base Address) Reserved (Base Address) Reserved SUBVENDID SUBDEVID RBASE Subsystem Vendor ID Register Subsystem Device ID Register ROM Base Address Register Reserved Reserved INTLINE INTPIN Interrupt Line Register Interrupt Pin Register Reserved (Minimum Grant) Reserved (Maximum Latency) SUBVENDSET SUBDEVSET Subsystem Vendor ID Set Register Subsystem Device ID Set Register Access read-only read-only read/clear read-only read-only read-only read-only read-only -- -- -- -- read/write -- -- -- -- -- -- read-only read-only read/write -- -- read/write read-only -- -- read/write read/write Bits 16 16 16 16 8 8 8 8 8 8 8 8 32 32 32 32 32 32 32 16 16 32 32 32 8 8 8 8 16 16 Configuration Space Offset 00 02 04 06 08 09 0A 0B 0C 0D 0E 0F 10 14 18 1C 20 24 28 2C 2E 30 34 38 3C 3D 3E 3F 40 to 6B 6C 6E 6F to FF
Note: The mechanism used to generate the PCI configuration read and configuration write cycles by which these registers are accessed is system-dependent.
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7-2
PCI Configuration Registers
VENDID
15 14 13
Vendor ID Register
12 11 10 9 8 7 6 5 4 3 2 1 0
read-only at PCI configuration offset 00h byte or word accessible accessible only via PCI configuration cycles
Vendor ID (102Ch)
15-0
Vendor ID This is the vendor ID assigned by the PCI Special Interest group. This register always returns the 16-bit value 102Ch (4140 decimal).
DEVID
15 14
Device ID Register
13 12 11 10 9 8 7 6 5 4 3 2 1 0
read-only at PCI configuration offset 02h byte or word accessible accessible only via PCI configuration cycles
Device ID (0C30h)
15-0
Device ID This is the device ID assigned to this graphics controller. This register always returns the 16-bit value 0C30h when read.
efmp69030 Databook
Revision 1.3 11/24/99
PCI Configuration Registers
7-3
DEVCTL
15 14 13
Device Control Register
12 11 10 9 8 7
Wait Cycl Ctl (1)
read/write at PCI configuration offset 04h byte or word accessible accessible only via PCI configuration cycles
6
PERR Enbl (0)
5
VGA Pal Snoop (0)
4
Mem Wrt / Inval. (0)
3
Spec Cycl (0)
2
Bus Mstr (0)
1
Mem Acc (0)
0
I/O Acc (0)
Reserved
Fast SERR Bk-Bk Enbl (0) (0)
(0000:00)
15-10 9
Reserved Each of these bits always return a value of 0 when read. Fast Back-to-Back Enable for Masters This bit applies only to PCI Bus masters. Since this graphics controller never functions as a PCI Bus master, this bit always returns a value of 0 when read. SERR# Enable 0: Disables the use of SERR# and the setting of bit 14 (Signaled System Error bit) in the Device Status Register (DEVSTAT) to 1 as a response to an address parity error. This is the default after reset. 1: Enables the use of SERR# and the setting of bit 14 (Signaled System Error bit) in the Device Status Register (DEVSTAT) to 1 as a response to an address parity error. Wait Cycle Control This bit controls enables and disables address stepping. Since this graphics controller always supports address stepping, this bit always returns a value of 1 when read. Parity Error Response 0: Disables the use of PERR# as a response to detecting either data or address parity errors. Disables the setting of bit 14 (Signaled System Error bit) in the Device Status Register (DEVSTAT) to 1 as a response to an address parity error. This is the default after reset. 1: Enables the use of PERR# as a response to detecting either data or address parity errors. Enables the setting of bit 14 (Signaled System Error bit) in the Device Status Register (DEVSTAT) to 1 as a response to an address parity error. Note: Bit 8 (SERR# Enable) of this register must also be set to 1 to enable the use of SERR# and the setting of bit 14 (Signaled System Error bit) in the Device Status Register (DEVSTAT) to 1 as a response to an address parity error.
8
7
6
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7-4 5
PCI Configuration Registers VGA Palette Snoop 0: Accesses to all VGA I/O locations including those for the palette will be claimed. All read and write accesses to the palette will be performed normally. This is the default after reset. 1: Accesses to all VGA I/O locations, except for those for the palette, will be claimed. All reads will be entirely ignored, but all writes will still update the palette. This permits accesses to the palette I/O addresses to be answered by other devices that need to be able to snoop accesses to the palette. Memory Write & Invalidate This bit applies only to PCI Bus masters. Since this graphics controller never functions as a PCI Bus master, this bit always returns a value of 0 when read. Special Cycles This graphics controller always ignores all special cycles, therefore this bit always returns the value of 0 when read. Bus Master This graphics controller never functions as a PCI Bus master, therefore this bit always returns a value of 0 when read. Memory Access Enable 0: Disables access to the frame buffer memory locations within the range specified by the MBASE Register. This is the default after reset. 1: Enables access to the frame buffer memory locations within the range specified by the MBASE Register. Note: Accesses with only adjacent active byte enables are supported.
4
3
2
1
0
I/O Access Enable 0: Disables I/O port accesses. This is the default after reset. 1: Enables I/O port accesses. Note: Accesses with only adjacent active byte enables are supported.
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PCI Configuration Registers
7-5
DEVSTAT
Device Status Register
read/write at PCI configuration offset 06h byte or word accessible accessible only via PCI configuration cycles
15 14 13 12 11 10 9 8 Data Parity Error (0) 7 Fast BackBack (1) 6 UDF 5 66 MHz (1) 4 3 2 Reserved 1 0 Signal Rcvd Rcvd Signal Det Parity System Master Target Target Error Error Abort Abort Abort (0) (0) (0) (0) (0) DEVSEL# Timing (01)
(0)
(0:0000)
Important: Read accesses to this register behave normally. Writes, however, behave differently in that bits can be reset to 0, but not set to 1. A bit in this register is reset to 0 whenever it is written with the value of 1. Bits written with a value of 0 are entirely unaffected. 15 Detected Parity Error 0: No address or data parity error detected. 1: An address or data parity error was detected. Note: This bit is set in response to a parity error regardless of the settings of either bit 6 (Parity Error Response bit) and 8 (SERR# Enable) of the Device Control Register (DEVCTL). 14 Signaled System Error 0: SERR# has not been asserted. 1: SERR# has been asserted. Note: Both bits 6 (Parity Error Response bit) and 8 (SERR# Enable) of the Device Control Register (DEVCTL) must both be set to 1 to enable the use of SERR# and the setting of this bit to 1 in response to an address parity error. 13 Received Master Abort This bit applies only to PCI Bus masters. Since this graphics controller never functions as a PCI Bus master, this bit always returns a value of 0 when read. Received Target Abort This bit applies only to PCI Bus masters. Since this graphics controller never functions as a PCI Bus master, this bit always returns a value of 0 when read. Signaled Target Abort 0: A target abort was not generated. 1: A target abort was generated. A target abort can be generated by this graphics controller on I/O cycles with non-adjacent active byte enables.
12
11
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PCI Configuration Registers DEVSEL# Timing These two bits specify the longest-possible amount of time that this graphics controller will take in decoding an address and asserting DEVSEL#. These two bits always return a value of 01, indicating a medium-length timing. Data Parity Error Detected This bit applies only to PCI Bus masters. Since this graphics controller never functions as a PCI Bus master, this bit always returns a value of 0 when read. Fast Back-to-Back Capable This bit always returns a value of 1 when read, indicating that this graphics controller is capable of fast back-to-back transactions that are not in the same segment. UDF Supported This bit always returns a value of 0 when read, indicating that this graphics controller does not provide features that are definable by the end-user. 66MHz Capable This bit always returns a value of 1 when read, indicating that this graphics controller can be used with PCI at a bus speed up to 66MHz. This graphics controller is compatible with the AGP bus as a device capable of frame-based AGP transfers, only, but it is NOT compatible with PCI-66 (the 66MHz version of PCI first described in revision 2.1 of the PCI specification from the PCI SIG). The setting of this bit has NO bearing on AGP compatibility -- this bit is entirely ignored by AGP device configuration firmware.
8
7
6
5
4-0
Reserved Each of these bits always return a value of 0 when read.
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PCI Configuration Registers
7-7
REV
7
Revision ID Register
6 5 4 3 2 1 0
read-only at PCI configuration offset 08h byte accessible accessible only via PCI configuration cycles
Chip Manufacturing Code (xxxx) Chip Revision Code (xxxx)
Note: 7-4 3-0
This register is identical to the Revision ID Register (XR04). Chip Manufacturing Code These four bits carry the fabrication code. Chip Revision Code These four bits carry the revision code. Revision codes start at 0 and are incremented for each new silicon revision.
PRG
7
Register-Level Programming Interface Register
6 5 4 3 2 1 0
read-only at PCI configuration offset 09h byte accessible accessible only via PCI configuration cycles
Register-Level Programming Interface (00h)
7-0
Register-Level Programming Interface This register always returns a value of 00h to identify this PCI device as a display controller with a VGA-compatible programming interface (as opposed to 01h, which would indicate a display controller with a 8514/A-compatible programming interface).
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PCI Configuration Registers
SUB
7
Sub-Class Code Register
6 5 4 3 2 1 0
read-only at PCI configuration offset 0Ah byte accessible accessible only via PCI configuration cycles
Sub-Class Code (00h)
7-0
Sub-Class Code This register always returns a value of 00h to identify this PCI device as a display controller of the VGA or 8514/A type.
BASE
7
Base Class Code Register
6 5 4 3 2 1 0
read-only at PCI configuration offset 0Bh byte accessible accessible only via PCI configuration cycles
Base Class Code (03h)
7-0
Base Class Code This register always returns a value of 03h to identify this PCI device as a display controller.
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PCI Configuration Registers
7-9
HDR
7 Single/Multi Function Dev (0)
Header Type Register
6 5 4 3 Reserved (000:0000) 2 1 0
read-only at PCI configuration offset 0Eh byte accessible accessible only via PCI configuration cycles
7
Single/Multiple Function Device This bit always returns a value of 0 when read, indicating that this PCI device is a singlefunction device, not a multi-function device. Reserved Each of these bits always return a value of 0 when read.
6-0
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PCI Configuration Registers
MBASE
31 30 29
Memory Base Address Register
28 27 26 25 24 23 22 21 20 19 18 17 16
read/write at PCI configuration offset 10h byte, word, or doubleword accessible accessible only via PCI configuration cycles
Memory Space Base Address (0000:0000) 15 14 13 12 11 10 9 8 7 6 5 Memory Space Size (0000:0000) 4 3 Pref. (0) 2 1 0 M or I/O (0)
Memory Space Size (0000:0000:0000)
Memory Type (00)
31-24
Memory Space Base Address These 8 bits select the base address for this 16MB memory space used by this graphics controller for the memory mapped registers and linear accesses to the frame buffer. Memory Space Size These 20 bits always return 0 to indicate that the size of this memory space is 16MB. Prefetchable This bit always returns a value of 0 when read, indicating that the data in this 16MB memory space should not be prefetched by the CPU. Memory Type These 2 bits always return values of 0 when read, indicating that this 16MB memory space may be placed anywhere in the system's 32-bit address space by the system's PCI configuration software. Memory/IO Space Indicator This bit always returns a value of 0 when read, indicating that this is a memory space, not an I/O space.
23-4 3
2-1
0
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PCI Configuration Registers
7-11
SUBVENDID
15 14 13 12
Subsystem Vendor ID Register
11 10 9 8 7 6 5 4 3 2 1 0
read-only at PCI configuration offset 2Ch byte or word accessible accessible only via PCI configuration cycles
Subsystem Vendor ID (102Ch)
15-0
Subsystem Vendor ID These bits are intended to carry the vendor ID of the vendor of the subsystem in which this graphics controller is used, such as an add-in graphics card. After reset, this register defaults to 102Ch, the vendor ID assigned by the PCI special interest group. The vendor ID of the actual subsystem vendor must be programmed into this graphics controller by writing it to the SUBVENDSET register in the PCI configuration space at offset 6Ch.
SUBDEVDID
15 14 13 12
Subsystem Device ID Register
11 10 9 8 7 6 5 4 3 2 1 0
read-only at PCI configuration offset 2Eh byte or word accessible accessible only via PCI configuration cycles
Subsystem Device ID (03C0h)
15-0
Subsystem Vendor ID These bits are intended to carry the device ID of the vendor of the subsystem in which this graphics controller is used, such as an add-in graphics card. After reset, this register defaults to 03C0h, the vendor ID assigned to this graphics controller. The device ID desired by actual subsystem vendor must be programmed into this graphics controller by writing it to the SUBDEVSET register in the PCI configuration space at offset 6Eh.
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PCI Configuration Registers
INTLINE
7
Interrupt Line Register
6 5 4 Interrupt Line (00h) 3 2 1 0
read/write at PCI configuration offset 3Ch byte accessible accessible only via PCI configuration cycles
7-0
Interrupt Line This register carries the level number of the interrupt line to which the interrupt output is routed by the host system. The graphics controller does not use the information in this register. The data is normally written to with the value determined by the host system's POST code, and then later read by other software to find out which interrupt level on the host CPU should be `hooked' by interrupt software.
INTPIN
7
Interrupt Pin Register
6 5 4 Interrupt pin (01h) 3 2 1 0
read-only at PCI configuration offset 3Dh byte accessible accessible only via PCI configuration cycles
7-0
Sub-class Code This register always returns a value of01h to indicate that the interrupt output should be connected to the INTA# signal.
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PCI Configuration Registers
7-13
RBASE
31 30 29
ROM Base Address Register
28 27 26 25 24 23 22 21 20 19 18 17 16
read/write at PCI configuration offset 30h byte, word, or doubleword accessible accessible only via PCI configuration cycles
ROM Space Base Address (0000:0000:0000:00) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ROM Space Size (00) 1 0 Addr Enbl (0)
ROM Space Size (0000:0000:0000:000)
31-18
ROM Space Base Address These 14 bits select the base address for this 256KB ROM space used by this graphics controller for the video BIOS ROM. ROM Space Size These 17 bits always return 0 to indicate that the size of this ROM space is 256KB. Address Decode Enable 0: Disable access to the video BIOS ROM. This is the default after reset. 1: Enable access to the video BIOS ROM. Note: Bit 1 of the Device Control register (DEVCTL) must also be set to 1 for the video BIOS ROM to be accessible. Also, the ROM address space must not be programmed to a range that overlaps the area specified by the MBASE register.
17-1 0
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PCI Configuration Registers
SUBVENDSET
15 14 13 12
Subsystem Vendor ID Set Register
11 10 9 8 7 6 5 4 3 2 1 0
read/write at PCI configuration offset 6Ch byte or word accessible accessible only via PCI configuration cycles
Subsystem Vendor ID Set (102Ch)
15-0
Subsystem Vendor ID Set These bits are used to program the vendor ID of the vendor of the subsystem in which this graphics controller is used, such as an add-in graphics card. After reset, this register defaults to 102Ch, the vendor ID assigned by the PCI special interest group. The vendor ID of the actual subsystem vendor must be programmed into the graphics controller by writing it to this register.
SUBDEVSET
15 14 13 12
Subsystem Device ID Set
11 10 9 8 7 6 5 4 3 2 1 0
read/write at PCI configuration offset 6Eh byte or word accessible accessible only via PCI configuration cycles
Subsystem Device ID Set (03C0h)
15-0
Subsystem Device ID Set These bits are intended to program the device ID specified by the vendor of the subsystem in which this graphics controller is used, such as an add-in graphics card. After reset this register defaults to 03C0h, the device ID assigned to this graphics controller. The device ID desired by the actual subsystem vendor must be programmed into this graphics controller by writing it to this register.
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General Control and Status Registers
8-1
Chapter 8 General Control and Status Registers
Introduction
Chapter 8 describes the General Control and Status Registers for the 69030 Dual HiQVideo Accelerator. These are direct-access registers. They are NOT read from or written to using any form of sub-indexing scheme. Table 8-1:
Name ST00 ST01 FCR MSR IOSS MSS
General Control and Status Registers
Function Input Status Register 0 Input Status Register 1 Feature Control Register Miscellaneous Output Register I/O Space Shadowing Register (shared) Memory Shadowing Register (shared) Read 3C2h 3BAh/3DAh 3CAh 3CCh 3CDh 3CBh Write -- -- 3BAh/3DAh 3C2h 3CDh 3CBh
Various bits in these registers have bits that provide control over the real-time status of the horizontal sync signal, the horizontal retrace interval, the vertical sync signal, and the vertical retrace interval. The horizontal retrace interval is the time when the drawing of each horizontal line has active video data, when the active video data is not being displayed. It is the time that includes the horizontal front and back porches, and the horizontal sync pulse. The horizontal retrace interval is always longer than the horizontal sync pulse. The vertical retrace interval is the period during the drawing of each screen, when the horizontal lines with active video data are not drawn. This period includes the vertical front and back porches, and the vertical sync pulse. The vertical retrace interval is always longer than the vertical sync pulse. The `Display Enable' status bit (bit 0) in Input Status Register 1 indicates that either a horizontal retrace interval or a vertical retrace interval is in progress (the name `Display Enable' is misleading for this status bit because the bit does not enable nor disable the graphics system as it's name suggests). In the IBM EGA graphics system (and the ones that preceded it, including MDA and CGA) it was important to check the status of this bit to ensure that one or the other of the retrace intervals was taking place before accessing the graphics memory. In these earlier systems reading from or writing to graphics memory outside the retrace intervals meant that the CRT controller would be cut off from accessing the graphics memory in order to draw pixels to the display, resulting in either "snow" or a flickering display.
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General Control and Status Registers
ST00
7 A B
Input Status Register 0
6 5 4 DAC CRT Sense 3 2 1 0
read-only at I/O Address 3C2h partially shared and partially shadowed between both pipelines A and B as shown
PIpe A Vert Ret Interrupt PIpe B Vert Ret Interrupt
Reserved
Reserved
7
Vertical Retrace Interrupt 0: Indicates that a vertical retrace interrupt is not pending. 1: Indicates that a vertical retrace interrupt is pending. Note: This bit does NOT indicate the status of any real hardware interrupt occurring at the onset of vertical retrace. This bit works in conjunction with bit 3 of ST01 and bits 4 and 5 of CR11 to implement a "phantom" interrupt for the sake of compatibility with older software. Early VGA graphics systems (and their predecessors, including the EGA) had the ability to generate a hardware interrupt on IRQ9 whenever a vertical retrace commenced. This was done because in these earlier graphics systems it was important for the host CPU to wait for a vertical retrace interval before accessing the frame buffer. If the host CPU accessed the frame buffer at a time other than the vertical retrace interval, i.e., while data for the active display area was being drawn to the display, then either "snow" on the display or a flickering display would result. Later graphics systems, including this one, do NOT actually generate this interrupt.
6-5 4
Reserved These bits return the value of 0 when read. DAC CRT Sense Indicates the state of the DAC analog output comparators. The comparators can be used to determine whether a CRT is currently attached, and/or whether the CRT is color or monochrome. This is done by blanking the CRT outputs, which causes the color value stored at index 0 in the color lookup table of the RAMDAC to be continuously output to the CRT. Different color values can then be written to the color lookup table at index 0 to set different output levels for the red, green and blue D-to-A converters.
Result 0 1 When Testing for Presence of CRT No CRT is present. CRT is present. When Testing for Color or Monochrome CRT Monochrome CRT. Color CRT.
3-0
Reserved These bits return the value of 0 when read.
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General Control and Status Registers
8-3
ST01
7 A B
Input Status Register 1
6 Reserved Reserved 5 4 3 Vertical Retrace Vertical Retrace 2 Reserved Reserved 1 0 Display Enable Display Enable
read-only at I/O Address 3BAh/3DAh shadowed between both pipelines A and B
VSYNC Output VSYNC Output Video Feedback 1,0 Video Feedback 1,0
7
VSYNC Output 0: The VSYNC output pin is currently inactive. 1: The VSYNC output pin is currently active. Note: This bit is largely unused by current software. Reserved This bit returns the value of 0 when read. Video Feedback 1, 0 These are diagnostic video bits that are programmably connected to two of the eight color bits sent to the palette. Bits 4 and 5 of the Color Plane Enable Register (AR12) select which two of the eight possible color bits become connected to these 2 bits of this register. The current software normally does not use these 2 bits. They exist for EGA compatibility. Vertical Retrace 0: Indicates that a vertical retrace interval is not taking place. 1: Indicates that a vertical retrace interval is taking place. Reserved These bits return the value of 0 when read. Display Enable 0: Data for the active display area is being drawn to the display. Neither a horizontal retrace interval nor a vertical retrace interval is currently taking place. 1: Either a horizontal or vertical retrace interval is currently taking place.
6 5-4
3
2-1 0
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General Control and Status Registers
FCR
7 A B
Feature Control Register
6 Reserved Reserved 5 4 3 VSYNC Control VSYNC Control 2 1 Reserved Reserved 0
write at I/O Address 3BAh/3DAh read at I/O Address 3CAh shadowed between both pipelines A and B
7-4 3
Reserved These bits return the value of 0 when read. VSYNC Control 0: VSYNC output pin simply provides the vertical sync signal. 1: VSYNC output pin provides a signal that is the logical OR of the vertical sync signal and the value of bit 0 of Input Status Register 1 (ST01). Note: This feature is largely unused by current software -- this bit is provided solely for VGA compatibility.
2-0
Reserved These bits return the value of 0 when read.
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General Control and Status Registers
8-5
MSR
7 A B
Miscellaneous Output Register
6 5 Page Select (0) 4 Reserved (0) 3 2 1 0
write at I/O Address 3C2h read at I/O Address 3CCh partially shared and partially shadowed between both pipelines A and B as shown
PIpe A Sync Output Pol (00) PIpe B Sync Output Pol (00) Pipe A Clock Select (00) Pipe B Clock Select (00)
RAM Enable I/O Address (0) (0)
7-6
Sync Output Polarity Bit 7 controls the polarity of the VSYNC output, while bit 6 performs the same function for the HSYNC output. For both of these bits, a value of 0 sets the corresponding sync output for positive polarity, while a value of 1 chooses negative polarity. The original VGA standard was created at a time pre-dating the onset of multifrequency displays that examined clock rates or counted pulses to determine resolutions. Therefore, different combinations of positive and negative polarities on the sync outputs were used to set original VGA displays to any one of three modes (depicted in the table below). However, over time, numerous additional resolutions and alternate timings intended to improve upon the original VGA standard came to be widely used. In order to maintain compatibility with the VGA standard, the vast majority of these use HSYNC and VSYNC outputs that are both configured to be of positive polarity since this was the only choice left over as `reserved' in the original VGA standard.
Bit 76 00 VSYNC Output Polarity positive HSYNC Output Polarity positive
Vertical Resolution Selected Not used for standard VGA modes. Often used for extended modes regardless of the number of scanlines. For standard VGA modes with 400 scanlines. For standard VGA modes with 350 scanlines. For standard VGA modes with 480 scanlines.
01 10 11
positive negative negative
negative positive negative
5
Odd/Even Page Select 0: Selects the lower 64KB page. 1: Selects the upper 64KB page. Selects between two 64KB pages of frame buffer memory during standard VGA odd/even modes (modes 0h through 5h). Bit 1 of register GR06 can also program this bit in other modes. Reserved This bit returns the value of 0 when read.
4
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8-6 3-2
General Control and Status Registers Clock Select These two bits select the dot clock.
Bit 32 00 01 10 11 Selected Clock CLK0 -- default 25MHz (for standard VGA modes with a horizontal resolution of 320 or 640 pixels. CLK1 -- default 28MHz (for standard VGA modes with a horizontal resolution of 360 or 720 pixels. CLK2 (normally for all extended modes or at any time a flat panel display is used) (this selection was `reserved' in the original VGA standard) reserved
1
RAM Access Enable 0: Disables CPU access to frame buffer. 1: Enables CPU access to frame buffer. I/O Address Select 0: Sets the I/O address decode for ST01, FCR, and all CR registers to the 3Bx I/O address range (for MDPA emulation). 1: Sets the I/O address decode for ST01, FCR, and all CR registers to the 3Dx I/O address range (for CGA emulation).
0
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General Control and Status Registers
8-7
IOSS
7 A & B
I/O Space Shadowing Register
6 Reserved (000) 5 4 Index Write En (0) 3 Index A/B Select (0) 2 Register Rd Select (0) 1 0
read/write at I/O address 3CDh shared between both pipelines A and B
I/O Space Reg Write Sel & Read-Mode Ctrl (00)
Note: Regardless of the setting of ANY bit in THIS register, this register is ALWAYS both readable and writable from the I/O space. This register controls access to all registers accessible from the I/O space, except itself. FCR, MSR, MSS, ST00 and ST01 are all direct-access registers, and are therefore controlled differently from any of the subindexed registers. Also, the AR and DAC sub-indexed register groups do not have the ability to share the use of a single set of indices. Due to functional quirks imposed by VGA compatibility considerations, the sets of indices for these registers in each of the pipelines can be used only with the corresponding sets of sub-indexed registers also belonging to that pipeline. In contrast, VGA compatibility considerations forced fewer restrictions on the CR, GR and SR registers, and the same absence of restrictions exist with the FR, MR and XR registers which are Intel extensions. Read and write access to the direct-access registers (FCR, MSR, MSS, ST00 and ST01) is controlled entirely by bits 2 through 0 of this register. Bit 2 selects which pipeline's set of these direct-access registers will respond to read accesses. Bits 1 and 0 select which pipeline's set of these direct-access registers will be writable. Read and write access to the AR and DAC sub-indexed registers, as well as their indices, is controlled by bits 2 through 0 of this register - bits 4 and 3 in no way control access to these sub-indexed registers or their indices. Bit 2 selects which pipeline's set of these sub-indexed registers and corresponding indices will respond to read accesses. Bits 1 and 0 select which pipeline's set of these sub-indexed registers and corresponding indices will be writable. Read and write access to the CR, FR, GR, MR, SR and XR sub-indexed registers is controlled by bits 2 through 0 of this register. Read and write access to the indices for these sub-indexed registers is controlled by bits 4 and 3. Bit 2 selects which pipeline's set of these sub-indexed registers will respond to read accesses. Bits 1 and 0 select which pipeline's set of these sub-indexed registers will be writable. Bit 3 allows the independent selection of which pipeline's set of indices for these sub-indexed registers will be used in making accesses to the actual sub-indexed registers. Bit 4 allows the independent control of write access to whichever set of indices is selected by bit 3.
7-5
Reserved These bits always return the value of 0 when read.
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8-8 4
General Control and Status Registers Sub-indexed Register Index Write Enable This bit defaults to the value of 0 after reset. For the FCR, MSR, MSS, ST00 and ST01 registers: Since these are direct-access and not sub-indexed registers, this bit has no effect on these registers. For the CR sub-indexed register group: This bit has no effect on write accesses from the I/O space to the index of this subindexed register group on either pipeline. Instead, bits 1 and 0 of this register control write access to one or both shadows of the index along with write accesses to the actual sub-indexed registers. For the FR, GR, MR, SR and XR sub-indexed register groups: 0: Disables write accesses (read access is always enabled) from the I/O space to the indices of these sub-indexed register groups regardless of whichever pipeline is selected by bit 3 of this register. 1: Enables write accesses from the I/O space to the indices of these sub-indexed register groups of whichever pipeline is selected by bit 3 of this register. For the AR and DAC register groups: This bit has no effect on write accesses from the I/O space to the indices of these sub-indexed register groups of either pipeline. Instead, bits 1 and 0 of this register control write access to one or both shadows of these indices along with write accesses to the actual sub-indexed registers.
3
Sub-indexed Register Index A/B Select This bit defaults to the value of 0 after reset. For the FCR, MSR, MSS, ST00 and ST01 registers: Since these are direct-access and not sub-indexed registers, this bit has no effect on these registers. For the CR sub-indexed register group: This bit has no effect on the selection of which pipeline's index for this sub-indexed register group is used in making accesses to the actual sub-indexed registers. Instead, bits 2 through 0 select both which pipeline's set of these sub-indexed registers and index will be made accessible for read or write accesses. For the FR, GR, MR, SR and XR sub-indexed register groups: 0: Selects pipeline A's indices for these sub-indexed register groups to be used in making accesses to these sub-indexed registers from the I/O space, regardless of whether the actual sub-indexed registers being accessed belong to pipeline A or B, or are shared. 1: Selects pipeline B's indices for these sub-indexed register groups to be used in making accesses to these sub-indexed registers from the I/O space, regardless of whether the actual sub-indexed registers being accessed belong to pipeline A or B, or are shared. For the AR and DAC register groups: This bit has no effect on the selection of which pipeline's indices for these sub-indexed register groups are used in making accesses to the actual sub-indexed registers. Instead, bits 2 through 0 select both which pipeline's sets of these subindexed registers and their indices will be made accessible for read or write accesses.
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General Control and Status Registers 2 I/O Space Register Read Select This bit defaults to the value of 0 after reset.
8-9
For the FCR, MSR, MSS, ST00 and ST01 registers: 0: All of these direct-access registers that either belong to or are shared by pipeline A are made readable from the I/O space. None of these direct-access registers that belong exclusively to pipeline B are readable from the I/O space. 1: All of these direct-access registers that either belong to or are shared by pipeline B are made readable from the I/O space. None of these direct-access registers that belong exclusively to pipeline A are readable from the I/O space. For the CR sub-indexed register group: 0: The CR sub-indexed register group that belongs to pipeline A is made readable from the I/O space using pipeline A's index for this register group. Neither the CR sub-indexed register group that belongs to pipeline B, or its index, are readable from the I/O space. 1: The CR sub-indexed register group that belongs to pipeline B is made readable from the I/O space using pipeline B's index for this register group. Neither the CR sub-indexed register group that belongs to pipeline A, or its index, are readable from the I/O space. Note: Write access to the index for the CR sub-indexed register group must be enabled using bits 1 and 0 of this register, since this index is controlled in the same way as the CR sub-indexed registers. For the FR, GR, MR, SR and XR sub-indexed register groups: 0: All of these sub-indexed register groups that either belong to or are shared by pipeline A are made readable from the I/O space. None of these sub-indexed register groups that belong exclusively to pipeline B are readable from the I/O space. 1: All of these sub-indexed register groups that either belong to or are shared by pipeline B are made readable from the I/O space. None of these sub-indexed register groups that belong exclusively to pipeline A are readable from the I/O space. Note: Which pipeline's indices for these sub-indexed register groups are used in accessing the actual sub-indexed registers, and whether or not the selected indices are writable are controlled by bits 3 and 4, respectively, of this register. For the AR and DAC register groups: 0: The AR and DAC sub-indexed register groups that belong to pipeline A are made readable from the I/O space using pipeline A's indices for these register groups. Neither of these sub-indexed register groups that belong to pipeline B, or their indices, are readable from the I/O space. 1: The AR and DAC sub-indexed register groups that belong to pipeline B are made readable from the I/O space using pipeline B's indices for these register groups. Neither of these sub-indexed register groups that belong to pipeline A, or their indices, are readable from the I/O space. Note: Write access to the indices for the AR and DAC sub-indexed register groups must be enabled using bits 1 and 0 of this register, since these indices are controlled in the same way as the actual sub-indexed registers of these groups.
efmp69030 Databook
Revision 1.3 11/24/99
8-10 1-0
General Control and Status Registers I/O Space Register Write Select and Read-Mode Control These bits default to the value of 0 after reset. For the FCR, MSR, MSS, ST00 and ST01 registers:
Bit 10 00 01
Effect on Write Accesses to FCR, MSR, MSS, ST00 and ST01 All write access from the I/O space to these direct-access registers of both pipelines is disabled. Write access to these direct-access registers that either belong to or are shared by pipeline A are made writable from the I/O space. None of these direct-access registers that belong exclusively to pipeline B are writable from the I/O space. Write access to these direct-access registers that either belong to or are shared by pipeline B are made writable from the I/O space. None of these direct-access registers that belong exclusively to pipeline A are writable from the I/O space. Write access from the I/O space to these direct-access registers of both pipelines is enabled.
10
11
For the CR sub-indexed register group:
Bit 10 00 01
Effect on Write Accesses to CR Sub-indexed Register Group All write access from the I/O space to the CR sub-indexed register groups of both pipelines is disabled. The CR sub-indexed register group that belongs to pipeline A is made writable from the I/O space using pipeline A's index for this register group. Neither the CR sub-indexed register group that belongs to pipeline B, or its index, are readable from the I/O space. The CR sub-indexed register group that belongs to pipeline B is made writable from the I/O space using pipeline B's index for this register group. Neither the CR sub-indexed register group that belongs to pipeline A, or its index, are readable from the I/O space. Write access from the I/O space to the CR sub-indexed register groups of both pipelines is enabled.
10
11
Note: Write access to the index for the CR sub-indexed register group must be enabled using these 2 bits of this register, since this index is controlled in the same way as the actual CR sub-indexed registers, themselves.
efmp69030 Databook
Revision 1.3 11/24/99
General Control and Status Registers For the CR, FR, GR, MR, SR and XR sub-indexed register groups:
8-11
Bit 10 00 01
Effect on Write Accesses to FR, GR, MR, SR and XR Sub-indexed Register Groups All write access from the I/O space to these sub-indexed register groups of both pipelines is disabled. Write access to these sub-indexed register groups that either belong to or are shared by pipeline A are made writable from the I/O space. None of these sub-indexed register groups that belong exclusively to pipeline B are writable from the I/O space. Write access to these sub-indexed register groups that either belong to or are shared by pipeline B are made writable from the I/O space. None of these sub-indexed register groups that belong exclusively to pipeline A are writable from the I/O space. Write access from the I/O space to these sub-indexed register groups of both pipelines is enabled.
10
11
Note: Which pipeline's indices for these sub-indexed register groups are used in accessing the actual sub-indexed registers, and whether or not the selected indices are writable are controlled by bits 3 and 4, respectively, of this register.
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Revision 1.3 11/24/99
8-12
General Control and Status Registers For the AR and DAC sub-indexed register groups:
Bit 10 00 01
Effect on Write Accesses to AR and DAC Sub-indexed Register Groups All write access from the I/O space to these sub-indexed register groups of both pipelines is disabled. The AR and DAC sub-indexed register groups that belong to pipeline A are made writable from the I/O space using pipeline A's indices for these register groups. Neither the AR or DAC sub-indexed register groups that belong to pipeline B, or their indices, are writable from the I/O space. If bit 1 of pipeline A's shadow of XR09 is set to 0, then the index register for pipeline A's AR register group (ARX) toggles between being an index and a data port when written to, and reading from pipeline A's shadow of ST01 sets ARX to being an index. If bit 1 of pipeline A's shadow of XR09 is set to 1, then the index register for pipeline A's AR register group (ARX) remains locked as being only an index register.
10
The AR and DAC sub-indexed register groups that belong to pipeline B are made writable from the I/O space using pipeline B's indices for these register groups. Neither the AR or DAC sub-indexed register groups that belong to pipeline A, or their indices, are writable from the I/O space. If bit 1 of pipeline B's shadow of XR09 is set to 0, then the index register for pipeline A's AR register group (ARX) toggles between being an index and a data port when written to, and reading from pipeline B's shadow of ST01 sets ARX to being an index. If bit 1 of pipeline A's shadow of XR09 is set to 1, then the index register for pipeline A's AR register group (ARX) remains locked as being only an index register.
11
Write access from the I/O space to the AR and DAC subindexed register groups of both pipelines is enabled. For whichever pipeline wherein bit 1 of XR09 is set to 0, the index register for that pipeline's AR register group (ARX) toggles between being an index and a data port when written to, and reading from EITHER pipeline's shadow of ST01 will set it to being an index. For whichever pipeline wherein bit 0 of XR09 is set to 1, the index register for that pipeline's AR register group (ARX) remains locked as being only an index register.
Note: Write access to the indices for these two sub-indexed register groups must be enabled using these 2 bits of this register, since these indices are controlled in the same way as the actual sub-indexed registers of these groups.
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Revision 1.3 11/24/99
General Control and Status Registers
8-13
MSS
7 A & B
Memory Space Shadowing Register
6 Reserved (0000) 5 4 3 Mem Shad En (0) 2 A/B Reg Read (0) 1 Pipe A Reg Write (0) 0 Pipe B Reg Write (0)
read/write at I/O address 3CBh shared by both pipelines A and B
7-4 3
Reserved These bits always return the value of 0 when read. Memory Space Shadowing Enable 0: Disables memory space shadowing. All registers for pipeline A remain mapped to memory offsets 400000 through 7FFFFF. All registers for pipeline B remain mapped to memory offsets C00000 through FFFFFF. This is the default after reset. 1: Enables memory space shadowing. All shadows of all registers for either pipeline A or B (not both at the same time) are accessible at both memory offsets 400000 through 7FFFFF and C00000 through FFFFFF. The choice of which pipeline's registers are to be made accessible for reading or writing is controlled via bits 2 through 0 of this register. Pipeline A or B Register Read Select Note: This bit has no effect if bit 3 of this register is set to 0. 0: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline A are accessible for reading via both memory offsets 400000 through 7FFFFF and C00000 through FFFFFF, and those registers belonging exclusively to pipeline B are not. This is the default after reset. 1: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline B are accessible for reading via both memory offsets 400000 through 7FFFFF and C00000 through FFFFFF, and those registers belonging exclusively to pipeline A are not.
2
1
Pipeline A Register Write Enable Note: This bit has no effect if bit 3 of this register is set to 0. 0: If bit 3 of this register is set to 1, then the registers belonging exclusively to pipeline A are NOT accessible for writing via either memory offsets 400000 through 7FFFFF or C00000 through FFFFFF. This is the default after reset. 1: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline A are accessible for writing via memory offsets 400000 through 7FFFFF.
0
Pipeline B Register Write Enable Note: This bit has no effect if bit 3 of this register is set to 0. 0: If bit 3 of this register is set to 1, then the registers belonging exclusively to pipeline B are NOT accessible for writing via either memory offsets 400000 through 7FFFFF or C00000 through FFFFFF. This is the default after reset. 1: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline B are accessible for writing via memory offsets C00000 through FFFFFF.
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8-14
General Control and Status Registers
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CRT Controller Registers
9-1
Chapter 9 CRT Controller Registers
Introduction
The CRT controller registers are accessed by writing the index of the desired register into the CRT Controller Index Register at I/O address 3B4h or 3D4h (depending upon whether the graphics system is configured for MDA or CGA emulation), and then accessing the desired register through the data port for the CRT controller registers located at I/O address 3B5h or 3D5h (again depending upon the choice of MDA or CGA emulation)
Name CR00 CR01 CR02 CR03 CR04 CR05 CR06 CR07 CR08 CR09 CR0A CR0B CR0C CR0D CR0E CR0F CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR22 CR30 CR31 CR32 CR33 CR38 CR3C CR40 CR41 CR70 CR71 CR72 CR73 CR74 CR75 CR76 CR77 CR78 CR79 Register Function Horizontal Total Register Horizontal Display Enable End Register Horizontal Blanking Start Register Horizontal Blanking End Register Horizontal Sync Start Register Horizontal Sync End Register Vertical Total Register Overflow Register Preset Row Scan Register Maximum Scanline Register Text Cursor Start Scanline Register Text Cursor End Scanline Register Start Address High Register Start Address Low Register Text Cursor Location High Register Text Cursor Location Low Register Vertical Sync Start Register Vertical Sync End Register Vertical Display Enable End Register Offset Register Underline Row Register Vertical Blanking Start Register Vertical Blanking End Register CRT Mode Control Register Line Compare Register Memory Read Latch Data Register Extended Vertical Total Register Extended Vertical Display End Register Extended Vertical Sync Start Register Extended Vertical Blanking Start Register Extended Horizontal Total Register Extended Horizontal Blanking End Register Extended Start Address Register Extended Span Register (shadowed) Interlace Control Register NTSC/PAL Video Output Control Register NTSC/PAL Horizontal Serration 1 Start Register NTSC/PAL Horizontal Serration 2 Start Register NTSC/PAL Horizontal Pulse Width Register NTSC/PAL Filtering Burst Read Length Register NTSC/PAL Filtering Burst Read Quantity Register NTSC/PAL Filtering Control Register NTSC/PAL Vertical Reduction Register NTSC/PAL Pixel Resolution Fine Adjust Register Access 3B5/3D5 read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Index Value 3B4/3D4 (CRX) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 22h 30h 31h 32h 33h 38h 3Ch 40h 41h 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h
efmp69030 Databook
Revision 1.3 11/24/99
9-2
CRT Controller Registers
CRX
7 A B
CRT Controller Index Register
6 5 4 3 2 1 0
read/write at I/O address 3B4h/3D4h This register is cleared to 00h by reset. shadowed for pipelines A and B
CRT Controller Register Index CRT Controller Register Index
7-0
CRT Controller Register Index These 8 bits are used to select any one of the CRT controller registers to be accessed via the data port at I/O location 3B5h or 3D5h (depending upon whether the graphics system is configured for MDA or CGA emulation).
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Revision 1.3 11/24/99
CRT Controller Registers
9-3
CR00
7 A B
Horizontal Total Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 00h shadowed for pipelines A and B
Horizontal Total Horizontal Total
7-0
Horizontal Total These bits provide either all 8 bits of an 8-bit value or the least significant 8 bits of a 9-bit value that specifies the total length of a scanline. This includes both the part of the scanline that is within the active display area and the part that is outside of it. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the horizontal total is specified with an 8-bit value, 8 bits of which are supplied by this register. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the horizontal total is specified with a 9-bit value. The 8 least significant bits of the vertical total are supplied by the 8 bits of this register. The most significant bit is supplied by bit 0 of the Extended Horizontal Total Register (CR38). This 8-bit or 9-bit value should be programmed to equal the total number of character clocks within the total length of a scanline, minus 5. Note: For NTSC/PAL output support, CR79 can be used to add a programmable number of pixel clocks (as opposed to character clocks) to the horizontal total, permitting the horizontal total to be specified with greater precision.
CR01
7 A B
Horizontal Display Enable End Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at 3B4h/3D4h set to 01h shadowed for pipelines A and B
Horizontal Display Enable End Horizontal Display Enable End
7-0
Horizontal Display Enable End This register is used to specify the end of the part of the scanline that is within the active display area relative to its beginning. In other words, this is the horizontal width of the active display area. This register should be programmed with a value equal to the number of character clocks that occur within the part of a scanline that is within the active display area minus 1.
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Revision 1.3 11/24/99
9-4
CRT Controller Registers
CR02
7 A B
Horizontal Blanking Start Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 02h shadowed for pipelines A and B
Horizontal Blanking Start Horizontal Blanking Start
7-0
Horizontal Blanking Start This register is used to specify the beginning of the horizontal blanking period relative to the beginning of the active display area of a scanline. This register should be programmed with a value equal to the number of character clocks that occur on a scanline from the beginning of the active display area to the beginning of the horizontal blanking.
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Revision 1.3 11/24/99
CRT Controller Registers
9-5
CR03
7 A B
Horizontal Blanking End Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 03h shadowed for pipelines A and B
Reserved Reserved Display Enable Skew Control Display Enable Skew Control Horizontal Blanking End Bits 4-0 Horizontal Blanking End Bits 4-0
7
Reserved Values written to this bit are ignored. To maintain consistency with the VGA standard, a value of 1 is returned whenever this bit is read. At one time, this bit was used to enable access to certain light pen registers. At that time, setting this bit to 0 provided this access, but setting this bit to 1 was necessary for normal operation. Display Enable Skew Control Defines the degree to which the start and end of the active display area are delayed along the length of a scanline to compensate for internal pipeline delays. These 2 bits describe the delay in terms of a number character clocks.
Bit 65 00 01 10 11 no delay delayed by 1 character clock delayed by 2 character clocks delayed by 3 character clocks Amount of Delay
6-5
4-0
Horizontal Blanking End Bits 4-0 These 5 bits provide the 5 least significant bits of either a 6-bit or 8-bit value that specifies the end of the blanking period relative to its beginning on a single scanline. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the horizontal blanking end is specified with a 6-bit value. The 5 least significant bits of the horizontal blanking end are supplied by these 5 bits of this register, and the most significant bits is supplied by bit 7 of the Horizontal Sync End Register (CR05). In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the horizontal blanking end is specified with an 8-bit value. The 5 least significant bits of the horizontal blanking end are supplied by these 5 bits of this register, the next most significant bit is supplied by bit 7 of the Horizontal Sync End Register (CR05), and the 2 most significant bits are supplied by bits 7 and 6 of the Extended Horizontal Blanking End Register (CR3C). This 6-bit or 8-bit value should be programmed to be equal to the least significant 6 or 8 bits, respectively, of the result of adding the length of the blanking period in terms of character clocks to the value specified in the Horizontal Blanking Start Register (CR02).
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Revision 1.3 11/24/99
9-6
CRT Controller Registers
CR04
7 A B
Horizontal Sync Start Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 04h shadowed for pipelines A and B
Horizontal Sync Start Horizontal Sync Start
7-0
Horizontal Sync Start This register is used to specify the beginning of the horizontal sync pulse relative to the beginning of the active display area on a scanline. This register should be set to be equal to the number of character clocks that occur from the beginning of the active display area to the beginning of the horizontal sync pulse on a single scanline.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-7
CR05
7 A B
Horizontal Sync End Register
6 5 4 3 2 Horizontal Sync End Horizontal Sync End 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 05h shadowed for pipelines A and B
Hor Blnk End Bit 5 Hor Blnk End Bit 5 Horizontal Sync Delay Horizontal Sync Delay
7
Horizontal Blanking End Bit 5 This bit provides either the most significant bit of a 6-bit value or the 3rd most significant bit of an 8-bit value that specifies the end of the horizontal blanking period relative to its beginning. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the horizontal blanking end is specified with a 6-bit value. The 5 least significant bits of this value are supplied by bits 4-0 of the Horizontal Blanking End Register (CR03), and the most significant bit is supplied by this bit of this register. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the horizontal blanking end is specified with an 8-bit value. The 5 least significant bits of this value are supplied by bits 4-0 of the Horizontal Blanking End Register (CR03), the next most significant bit is supplied by this bit of this register, and the 2 most significant bits are supplied by bits 7 and 6 of the Extended Horizontal Blanking End Register (CR3C). This 6-bit or 8-bit value should be programmed to be equal to the least significant 6 or 8 bits, respectively, of the result of adding the length of the blanking period in terms of character clocks to the value specified in the Horizontal Blanking Start Register (CR02).
6-5
Horizontal Sync Delay These bits define the degree to which the start and end of the horizontal sync pulse are delayed to compensate for internal pipeline delays. These 2 bits describe the delay in terms of a number of character clocks.
Bit 65 00 01 10 11 Amount of Delay no delay delayed by 1 character clock delayed by 2 character clocks delayed by 3 character clocks
4-0
Horizontal Sync End These 5 bits provide the 5 least significant bits of a 6-bit value that specifies the end of the horizontal sync pulse relative to its beginning. In other words, this 6-bit value specifies the width of the horizontal sync pulse. Bit 7 of Horizontal Sync End Register (CR05) supplies the most significant bit. This 6-bit value should be set to the least significant 6 bits of the result of adding the width of the sync pulse in terms of character clocks to the value specified in the Horizontal Sync Start Register (CR04).
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Revision 1.3 11/24/99
9-8
CRT Controller Registers
CR06
7 A B
Vertical Total Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 06h shadowed for pipelines A and B
Vertical Total Bits 7-0 Vertical Total Bits 7-0
7-0
Vertical Total Bits These bits provide the 8 least significant bits of either a 10-bit or 12-bit value that specifies the total number of scanlines. This includes the scanlines both inside and outside of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical total is specified with a 10-bit value. The 8 least significant bits of the vertical total are supplied by these 8 bits of this register, and the 2 most significant bits are supplied by bits 5 and 0 of the Overflow Register (CR07). In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical total is specified with a 12-bit value. The 8 least significant bits of the vertical total are supplied by the 8 bits of this register (CR06). The 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Total Register (CR30). This 10-bit or 12-bit value should be programmed to equal the total number of scanlines minus 2.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-9
CR07
7 A B
Overflow Register
6 Vert Disp En Bit 9 Vert Disp En Bit 9 5 Vert Total Bit 9 Vert Total Bit 9 4 Line Cmp Bit 8 Line Cmp Bit 8 3 Vert Blnk Start Bit 8 Vert Blnk Start Bit 8 2 Vert Sync Start Bit 8 Vert Sync Start Bit 8 1 Vert Disp En Bit 8 Vert Disp En Bit 8 0 Vert Total Bit 8 Vert Total Bit 8
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 07h shadowed for pipelines A and B
Vert Sync Start Bit 9 Vert Sync Start Bit 9
7
Vertical Sync Start Bit 9 The vertical sync start is a 10-bit or 12-bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical sync start is specified with a 10-bit value. The 8 least significant bits of the vertical sync start are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the most and second-most significant bits are supplied by bit 7 and bit 2 of this register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical display end is specified with a 12-bit value. The 8 least significant bits of the vertical display end are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Sync Start Register (CR32) register. In extended modes, neither bit 7 nor bit 2 of this register are used. This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines from the beginning of the active display area to the start of the vertical sync pulse. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which the vertical sync pulse begins.
6
Vertical Display Enable End Bit 9 The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last scanline within the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical display enable end is specified with a 10-bit value. The 8 least significant bits of the vertical display enable are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the most and second-most significant bits are supplied by bit 6 and bit 1 of this register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical display enable end is specified with a 12-bit value. The 8 least significant bits of the vertical display enable are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Display End Enable Register (CR31). In extended modes, neither bit 6 nor bit 1 of this register are used. This 10-bit or 12-bit value should be programmed to be equal to the number of the last scanline within in the active display area. Since the active display area always starts on the 0th scanline, this number should be equal to the total number of scanlines within the active display area minus 1.
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Revision 1.3 11/24/99
9-10
CRT Controller Registers
5
Vertical Total Bit 9 The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes the scanlines both inside and outside of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical total is specified with a 10-bit value. The 8 least significant bits of the vertical total are supplied by bits 7-0 of the Vertical Total Register (CR06), and the most and secondmost significant bits are supplied by bit 5 and bit 0 of this register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical total is specified with a 12-bit value. The 8 least significant bits of the vertical total are supplied by bits 7-0 of the Vertical Total Register (CR06), and the 4 most significant bits are supplied by 3-0 bits of the Extended Vertical Total Register (CR30). In extended modes, neither bit 5 nor bit 0 of this register are used. This 10-bit or 12-bit value should be programmed to be equal to the total number of scanlines minus 2.
4
Line Compare Bit 8 This bit provides the second most significant bit of a 10-bit value that specifies the scanline at which the memory address counter restarts at the value of 0. Bit 6 of the Maximum Scanline Register (CR09) supplies the most significant bit, and bits 7-0 of the Line Compare Register (CR18) supply the 8 least significant bits. Normally, this 10-bit value is set to specify a scanline after the last scanline of the active display area. When this 10-bit value is set to specify a scanline within the active display area, it causes that scanline and all subsequent scanlines in the active display area to display video data starting at the very first byte of the frame buffer. The result is what appears to be a screen split into a top and bottom part, with the image in the top part being repeated in the bottom part. When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low Register (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom parts displaying different data. The top part will display whatever data exists in the frame buffer starting at the address specified in the two start address registers (CR0C and CR0D), while the bottom part will display whatever data exists in the frame buffer starting at the first byte of the frame buffer.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-11
3
Vertical Blanking Start Bit 8 The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical blanking start is specified with a 10-bit value. The 8 least significant bits of the vertical blanking start are supplied by bits 7-0 of the Vertical Blanking Start Register (CR15), and the most and second-most significant bits are supplied by bit 5 of the Maximum Scanline Register (CR09) and bit 3 of this register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical blanking start is specified with a 12-bit value. The 8 least significant bits of the vertical blanking start are supplied by bits 7-0 of the Vertical Blanking Start Register (CR15), and the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Blanking Start Register (CR33). In extended modes, neither bit 3 of CR07 nor bit 5 of the Maximum Scanline Register (CR09) are used. This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines from the beginning of the active display area to the beginning of the blanking period. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which the vertical blanking period begins.
2
Vertical Sync Start Bit 8 The vertical sync start is a 10-bit or 12-bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical sync start is specified with a 10-bit value. The 8 least significant bits of the vertical sync start are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the most and second-most significant bits are supplied by bit 7 and bit 2 of this register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical display end is specified with a 12-bit value. The 8 least significant bits of the vertical display are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Sync Start Register (CR32) register. In extended modes, neither bit 7 nor bit 2 of this register (CR07) are used. This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines from the beginning of the active display area to the start of the vertical sync pulse. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which the vertical sync pulse begins.
efmp69030 Databook
Revision 1.3 11/24/99
9-12
CRT Controller Registers
1
Vertical Display Enable End Bit 8 The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last scanline within the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical display enable end is specified with a 10-bit value. The 8 least significant bits of the vertical display enable are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the most and second-most significant bits are supplied by bit 6 and bit 1 of this register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical display enable end is specified with a 12-bit value. The 8 least significant bits of the vertical display enable are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Display End Enable Register (CR31). In extended modes, neither bit 6 nor bit 1 of this register (CR07) are used. This 10-bit or 12-bit value should be programmed to be equal to the number of the last scanline within in the active display area. Since the active display area always starts on the 0th scanline, this number should be equal to the total number of scanlines within the active display area minus 1.
0
Vertical Total Bit 8 The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes the scanlines both inside and outside of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical total is specified with a 10-bit value. The 8 least significant bits of the vertical total are supplied by bits 7-0 of the Vertical Total Register (CR06), and the most and secondmost significant bits are supplied by bit 5 and bit 0 of this register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical total is specified with a 12-bit value. The 8 least significant bits of the vertical total are supplied by bits 7-0 of the Vertical Total Register (CR06), and the 4 most significant bits are supplied by 3-0 bits of the Extended Vertical Total Register (CR30). In extended modes, neither bit 5 nor bit 0 of this register (CR07) are used. This 10-bit or 12-bit value should be programmed to be equal to the total number of scanlines minus 2.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-13
CR08
7 A B
Preset Row Scan Register
6 5 4 3 2 Starting Row Scan Count Starting Row Scan Count 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 08h shadowed for pipelines A and B
Reserved Reserved Left Hor Pixel Shift Left Hor Pixel Shift
7 6-5
Reserved Leftward Horizontal Pixel Shift Bits 6 and 5 of this register hold a 2-bit value that selects number of bytes (up to 3) by which the image is shifted horizontally to the left on the screen. This function is available in both text and graphics modes. In text modes with a 9-pixel wide character box, the image can be shifted up to 27 pixels to the left, in increments of 9 pixels. In text modes with an 8-pixel wide character box, and in all standard VGA graphics modes, the image can be shifted up to 24 pixels to the left in increments of 8 pixels. The image can be shifted still further, in increments of individual pixels, through the use of bits 3-0 of the Horizontal Pixel Panning Register (AR13).
Number of Pixels Shifted Bit 65 00 01 10 11 9-Pixel Text 0 9 18 27 8-Pixel Text & Graphics 0 8 16 24
Note: In the VGA standard this is called the `Byte Panning' bit. 4-0 Starting Row Scan Count These 5 bits specify which horizontal line of pixels within the character boxes of the characters used on the top-most row of text on the display will be used as the top-most scanline. The horizontal lines of pixels of a character box are numbered from top to bottom, with the top-most line of pixels being number 0. If a horizontal line of these character boxes other than the top-most line is specified, then the horizontal lines of the character box above the specified line of the character box will not be displayed as part of the top-most row of text characters on the display. Normally the value specified by these 5 bits should be 0, so that all of the horizontal lines of pixels within these character boxes will be displayed in the top-most row of text, ensuring that the characters in the top-most row of text do not look as though they have been cut off at the top.
efmp69030 Databook
Revision 1.3 11/24/99
9-14
CRT Controller Registers
CR09
7 A B
Maximum Scanline Register
6 Line Cmp Bit 9 Line Cmp Bit 9 5 Vert Blnk Start Bit 9 Vert Blnk Start Bit 9 4 3 2 Maximum Scanline Maximum Scanline 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 09h shadowed for pipelines A and B
Double Scanning Double Scanning
7
Double Scanning 0: Disables double scanning. The clock to the row scan counter is equal to the horizontal scan rate. This is the normal setting for many of the standard VGA modes and all of the extended modes. 1: Enables double scanning. The clock to the row scan counter is divided by 2. This is normally used to allow CGA-compatible modes that have only 200 scanlines of active video data to be displayed as 400 scanlines (each scanline is displayed twice). Line Compare Bit 9 This bit provides the most significant bit of a 10-bit value that specifies the scanline at which the memory address counter restarts at the value of 0. Bit 4 of the Overflow Register (CR07) supplies the second most significant bit and bits 7-0 of the Line Compare Register (CR18) supply the 8 least significant bits. Normally, this 10-bit value is set to specify a scanline after the last scanline of the active display area. When this 10-bit value is set to specify a scanline within the active display area, it causes that scanline and all subsequent scanlines in the active display area to display video data starting at the very first byte of the frame buffer. The result is what appears to be a screen split into a top and bottom part, with the image in the top part being repeated in the bottom part. When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low Register (CR0D), it is possible to create a split display but with the top and bottom parts displaying different data, as described earlier. The top part will display whatever data exists in the frame buffer starting at the address specified in the two start address registers (CR0C and CR0D) while the bottom part will display whatever data exists in the frame buffer starting at the first byte of the frame buffer.
6
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers 5
9-15
Vertical Blanking Start Bit 9 The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical blanking start is specified with a 10-bit value. The 8 least significant bits of the vertical blanking start are supplied by bits 7-0 of the Vertical Blanking Start Register (CR15) and the most and second-most significant bits are supplied by bit 5 of this register (CR09) and bit 3 of the Overflow Register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical blanking start is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits 7-0 of the Vertical Blanking Start Register (CR15), and the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Blanking Start Register (CR33). In extended modes, neither bit 5 of CR09 nor bit 3 of the Overflow Register (CR07) are used. This 10-bit or 12-bit value should be programmed to be equal to the number of scanline from the beginning of the active display area to the beginning of the blanking period. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which the vertical blanking period begins.
4-0
Starting Row Scan Count These bits provide all 5 bits of a 5-bit value that specifies the number of scanlines in a horizontal row of text. This value should be programmed to be equal to the number of scanlines in a Horizontal row of text, minus 1.
efmp69030 Databook
Revision 1.3 11/24/99
9-16
CRT Controller Registers
CR0A
7 A B
Text Cursor Start Register
6 Reserved Reserved 5 Text Cursor Off Text Cursor Off 4 3 2 Text Cursor Start Text Cursor Start 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Ah shadowed for pipelines A and B
This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup (cursor 1 and cursor 2), which are intended to be used in graphics modes. This register is entirely ignored in graphics modes. 7-6 5 Reserved Text Cursor Off 0: Enables the text cursor. 1: Disables the text cursor. Text Cursor Start These 5 bits specify which horizontal line of pixels within a character box is to be used to display the first horizontal line of the cursor in text mode. The horizontal lines of pixels within a character box are numbered from top to bottom, with the top-most line being number 0. The value specified by these 5 bits should be the number of the first horizontal line of pixels on which the cursor is to be shown.
4-0
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-17
CR0B
7 A B Reserved Reserved
Text Cursor End Register
6 5 4 3 2 Text Cursor End Text Cursor End 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Bh shadowed for pipelines A and B
Text Cursor Skew Text Cursor Skew
This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup (cursor 1 and cursor 2), which are intended to be used in graphics modes. This register is entirely ignored in graphics modes. 7 6-5 Reserved Text Cursor Skew Specifies the degree to which the start and end of each horizontal line of pixels making up the cursor is delayed to compensate for internal pipeline delays. These 2 bits describe the delay in terms of a number of character clocks.
Bits 65 00 01 10 11 Amount of Delay no delay delayed by 1 character clock delayed by 2 character clocks delayed by 3 character clocks
4-0
Text Cursor End These 5 bits specify which horizontal line of pixels within a character box is to be used to display the last horizontal line of the cursor in text mode. The horizontal lines of pixels within a character box are numbered from top to bottom, with the top-most line being number 0. The value specified by these 5 bits should be the number of the last horizontal line of pixels on which the cursor is to be shown.
efmp69030 Databook
Revision 1.3 11/24/99
9-18
CRT Controller Registers
CR0C
7 A B
Start Address High Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Ch shadowed for pipelines A and B
Start Address Bits 15-8 Start Address Bits 15-8
7-0
Start Address Bits 15-8 This register provides bits 15 through 8 of either a 16-bit or 20-bit value that specifies the memory address offset from the beginning of the frame buffer at which the data to be shown in the active display area begins. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the start address is specified with a 16-bit value. The eight bits of this register provide the eight most significant bits of this value, while the eight bits of the Start Address Low Register (CR0D) provide the eight least significant bits. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the start address is specified with a 20-bit value. The four most significant bits are provided by bits 3-0 of the Extended Start Address Register (CR40), bits 15 through 8 of this value are provided by this register and the eight least significant bits are provided by the Start Address Low Register (CR0D). Note that in extended modes, these 20 bits are doublebuffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance. To change the start address in extended modes, all three registers must be set for the new value, and then bit 7 of CR40 must be set to 1. When this is done the hardware will update the start address on the next VSYNC. When this update has been performed, the hardware will set bit 7 of CR40 back to 0.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-19
CR0D
7 A B
Start Address Low Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Dh shadowed for pipelines A and B
Start Address Bits 7-0 Start Address Bits 7-0
7-0
Start Address Bits 7-0 This register provides the eight least significant bits of either a 16-bit or 20-bit value that specifies the memory address offset from the beginning of the frame buffer at which the data to be shown in the active display area begins. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the start address is specified with a 16-bit value. The eight bits of the Start Address High Register (CR0C) provide the eight most significant bits of this value, while the eight bits of this register provide the eight least significant bits. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the start address is specified with a 20-bit value. The four most significant bits are provided by bits 3-0 of the Extended Start Address Register (CR40), bits 15 through 8 of this value are provided by the Start Address High Register (CR0C), and the eight least significant bits are provided by this register. Note that in extended modes, these 20 bits are double-buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance. To change the start address in extended modes, all three registers must be set for the new value, and then bit 7 of CR40 must be set to 1. When this is done the hardware will update the start address on the next VSYNC. When this update has been performed, the hardware will set bit 7 of CR40 back to 0.
efmp69030 Databook
Revision 1.3 11/24/99
9-20
CRT Controller Registers
CR0E
7 A B
Text Cursor Location High Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Eh shadowed for pipelines A and B
Text Cursor Location Bits 15-8 Text Cursor Location Bits 15-8
This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup (cursor 1 and cursor 2), which are intended to be used in graphics modes. This register is entirely ignored in graphics modes. 7-0 Text Cursor Location Bits 15-8 This register provides the 8 most significant bits of a 16-bit value that specifies the address offset from the beginning of the frame buffer at which the text cursor is located. Bit 7-0 of the Text Cursor Location Low Register (CR0F) provide the 8 least significant bits.
CR0F
7 A B
Text Cursor Location Low Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Fh shadowed for pipelines A and B
Text Cursor Location Bits 7-0 Text Cursor Location Bits 7-0
This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup (cursor 1 and cursor 2), which are intended to be used in graphics modes. This register is entirely ignored in graphics modes. 7-0 Text Cursor Location Bits 7-0 This register provides the 8 least significant bits of a 16-bit value that specifies the address offset from the beginning of the frame buffer at which the text cursor is located. Bits 7-0 of the Text Cursor Location High Register (CR0E) provide the 8 most significant bits.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-21
CR10
7 A B
Vertical Sync Start Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 10h shadowed for pipelines A and B
Vertical Sync Start Bits 7-0 Vertical Sync Start Bits 7-0
7-0
Vertical Sync Start Bits 7-0 This register provides the 8 least significant bits of either a 10-bit or 12-bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active display area of a screen. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, this value is described in 10 bits with bits 7 and 2 of the Overflow Register (CR07) supplying the 2 most significant bits. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, this value is described in 12 bits with bits 3-0 of the Extended Vertical Sync Start Register (CR32) supplying the 4 most significant bits. This 10-bit or 12-bit value should equal the vertical sync start in terms of the number of scanlines from the beginning of the active display area to the beginning of the vertical sync pulse. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which the vertical sync pulse begins.
efmp69030 Databook
Revision 1.3 11/24/99
9-22
CRT Controller Registers
CR11
7 A B
Vertical Sync End Register
6 Reserved Reserved 5 Vert Int Enable Vert Int Enable 4 Vert Int Clear Vert Int Clear 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 11h shadowed for pipelines A and B
Protect Regs 0-7 Protect Regs 0-7 Vertical Sync End Vertical Sync End
7
Protect Registers 0-7 0: Enable writes to registers CR00-CR07. 1: Disable writes to registers CR00-CR07. Note: The ability to write to bit 4 of the Overflow Register (CR07) is not affected by this bit. Bit 4 of the Overflow Register is always writable.
6
Reserved Writes to this bit are ignored. In the VGA standard, this bit was used to switch between 3 and 5 frame buffer refresh cycles during the time required to draw each horizontal line. Vertical Interrupt Enable 0: Enable the generation of an interrupt at the beginning of each vertical retrace period. 1: Disable the generation of an interrupt at the beginning of each vertical retrace period. Note: The hardware does not actually provide an interrupt signal which would be connected to an input of the system's interrupt controller. Bit 7 of Input Status Register 0 (ST00) indicates the status of the vertical retrace interrupt, and can be polled by software to determine if a vertical retrace interrupt has taken place. Bit 4 of this register can be used to clear a pending vertical retrace interrupt.
5
4
Vertical Interrupt Clear Setting this bit to 0 clears a pending vertical retrace interrupt. This bit must be set back to 1 to enable the generation of another vertical retrace interrupt. Note: The hardware does not actually provide an interrupt signal which would be connected to an input of the system's interrupt controller. Bit 7 of Input Status Register 0 (ST00) indicates the status of the vertical retrace interrupt, and can be polled by software to determine if a vertical retrace interrupt has taken place. Bit 5 of this register can be used to enable or disable the generation of vertical retrace interrupts.
3-0
Vertical Sync End These 4 bits provide a 4-bit value that specifies the end of the vertical sync pulse relative to its beginning. This 4-bit value should be set to the least significant 4 bits of the result of adding the length of the vertical sync pulse in terms of the number of scanlines that occur within the length of the vertical sync pulse to the value that specifies the beginning of the vertical sync pulse. See the description of the Vertical Sync Start Register (CR10) for more details.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-23
CR12
7 A B
Vertical Display Enable End Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 12h shadowed for pipelines A and B
Vertical Display Enable End Bits 7-0 Vertical Display Enable End Bits 7-0
7-0
Vertical Display Enable End Bits 7-0 This register provides the 8 least significant bits of either a 10-bit or 12-bit value that specifies the number of the last scanline within the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, this value is described in 10 bits with bits 6 and 1 of the Overflow Register (CR07) supplying the 2 most significant bits. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, this value is described in 12 bits with bits 3-0 of the Extended Vertical Display Enable End Register (CR31) supplying the 4 most significant bits. This 10-bit or 12-bit value should be programmed to be equal to the number of the last scanline within in the active display area. Since the active display area always starts on the 0th scanline, this number should be equal to the total number of scanlines within the active display area, minus 1.
CR13
7 A B
Offset Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 13h shadowed for pipelines A and B
Offset Bits 7-0 Offset Bits 7-0
7-0
Offset Bits 7-0 This register provides either all 8 bits of an 8-bit value or the 8 least significant bits of a 12bit value that specifies the number of words or doublewords of frame buffer memory occupied by each horizontal row of characters. Whether this value is interpreted as the number of words or doublewords is determined by the settings of the bits in the Clocking Mode Register (SR01). In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the offset is described with an 8-bit value, with all the bits provided by this register (CR13). In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the offset is described with a 12-bit value. The four most significant bits of this value are provided by bits 3-0 of the Extended Offset Register (CR41), and the eight least significant bits are provided by this register (CR13). This 8-bit or 12-bit value should be programmed to be equal to either the number of words or doublewords (depending on the setting of the bits in the Clocking Mode Register, SR01) of frame buffer memory that is occupied by each horizontal row of characters.
efmp69030 Databook
Revision 1.3 11/24/99
9-24
CRT Controller Registers
CR14
7 A B
Underline Location Register
6 Dword Mode Dword Mode 5 Count By 4 Count By 4 4 3 2 Underline Location Underline Location 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 14h shadowed for pipelines A and B
Reserved Reserved
7 6
Reserved Doubleword Mode 0: Frame buffer addresses are interpreted by the frame buffer address decoder as being either byte addresses or word addresses, depending upon the setting of bit 6 of the CRT Mode Control Register (CR17). 1: Frame buffer addresses are interpreted by the frame buffer address decoder as being doubleword addresses regardless of the setting of bit 6 of the CRT Mode Control Register (CR17). Note: This bit is used in conjunction with bits 6 and 5 of the CRT Mode Control Register (CR17) to select how frame buffer addresses from the CPU are interpreted by the frame buffer address decoder as shown below:
CR14 Bit 6 0 0 1 1 CR17 Bit 6 0 1 0 1 Addressing Mode Word Mode Byte Mode Doubleword Mode Doubleword Mode
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers 5
9-25
Count By 4 0: The memory address counter is incremented either every character clock or every other character clock, depending upon the setting of bit 3 of the CRT Mode Control Register. 1: The memory address counter is incremented either every 4 character clocks or every 2 character clocks, depending upon the setting of bit 3 of the CRT Mode Control Register. Note: This bit is used in conjunction with bit 3 of the CRT Mode Control Register (CR17) to select the number of character clocks are required to cause the memory address counter to be incremented as shown, below:
CR14 Bit 5 0 0 1 1
CR17 Bit 3 0 1 0 1
Address Incrementing Interval every character clock every 2 character clocks every 4 character clocks every 2 character clocks
4-0
Underline Location These 5 bits specify which horizontal line of pixels in a character box is to be used to display a character underline in text mode. The horizontal lines of pixels within a character box are numbered from top to bottom, with the top-most line being number 0. The value specified by these 5 bits should be the number of the horizontal line on which the character underline mark is to be shown.
efmp69030 Databook
Revision 1.3 11/24/99
9-26
CRT Controller Registers
CR15
7 A B
Vertical Blanking Start Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 15h shadowed for pipelines A and B
Vertical Blanking Start Bits 7-0 Vertical Blanking Start Bits 7-0
7-0
Vertical Blanking Start Bits 7-0 This register provides the 8 least significant bits of either a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area of the screen. Whether this value is described in 10 or 12 bits depends on the setting of bit 0 of the I/O Control Register (XR09). In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical blanking start is specified with a 10-bit value. The most and second-most significant bits of this value are supplied by bit 5 of the Maximum Scanline Register (CR09) and bit 3 of the Overflow Register (CR07), respectively. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical blanking start is specified with a 12-bit value. The 4 most significant bits of this value are supplied by bits 3-0 of the Extended Vertical Blanking Start Register (CR33). This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines from the beginning of the active display area to the beginning of the vertical blanking period. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which vertical blanking begins, minus one.
CR16
7 A B
Vertical Blanking End Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 16h shadowed for pipelines A and B
Vertical Blanking End Bits 7-0 Vertical Blanking End Bits 7-0
7-0
Vertical Blanking End Bits 7-0 This register provides a 8-bit value that specifies the end of the vertical blanking period relative to its beginning. This 8-bit value should be set equal to the least significant 8 bits of the result of adding the length of the vertical blanking period in terms of the number of scanlines that occur within the length of the vertical blanking period to the value that specifies the beginning of the vertical blanking period (see the description of the Vertical Blanking Start Register for details).
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-27
CR17
7 A B
CRT Mode Control
6 Word or Byte Mode Word or Byte Mode 5 Address Wrap Address Wrap 4 Reserved Reserved 3 Count By 2 Count By 2 2 Horizontal Retrace Sel Horizontal Retrace Sel 1 Select Row Scan Cntr Select Row Scan Cntr 0 Compat Mode Supp. Compat Mode Supp.
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 17h shadowed for pipelines A and B
CRT Ctrl Reset CRT Ctrl Reset
7
CRT Controller Reset 0: Forces horizontal and vertical sync signals to be inactive. No other registers or outputs are affected. 1: Permits normal operation. Word Mode or Byte Mode 0: The memory address counter's output bits are shifted by 1 bit position before being passed on to the frame buffer address decoder such that they are made into word-aligned addresses when bit 6 of the Underline Location Register (CR17) is set to 0. 1: The memory address counter's output bits remain unshifted before being passed on to the frame buffer address decoder such that they remain byte-aligned addresses when bit 6 of the Underline Location Register (CR17) is set to 0. Note: This bit is used in conjunction with bits 6 and 5 of the CRT Mode Control Register (CR17) to control how frame buffer addresses from the memory address counter are interpreted by the frame buffer address decoder as shown below:
6
CR14 Bit 6 0 0 1 1
CR17 Bit 6 0 1 0 1
Addressing Mode Word Mode -- addresses from the memory address counter are shifted once to become word-aligned Byte Mode -- addresses from the memory address counter are not shifted Doubleword Mode -- addresses from the memory address counter are shifted twice to become doubleword-aligned Doubleword Mode -- addresses from the memory address counter are shifted twice to become doubleword-aligned
See the note at the end of this register description. 5 Address Wrap 0: Wrap frame buffer address at 16KB. This is used in CGA-compatible modes. 1: No wrapping of frame buffer addresses. Note: This bit is only effective when word mode is made active by setting bit 6 in both the Underline Location Register and this register to 0. See the note at the end of this register description. 4 Reserved
efmp69030 Databook
Revision 1.3 11/24/99
9-28 3
CRT Controller Registers Count By 2 0: The memory address counter is incremented either every character clock or every 4 character clocks, depending upon the setting of bit 5 of the Underline Location Register. 1: The memory address counter is incremented either every other clock. This bit is used in conjunction with bit 5 of the Underline Location Register (CR14) to select the number of character clocks required to cause the memory address counter to be incremented as shown, below:
CR14 Bit 5 0 0 1 1
CR17 Bit 3 0 1 0 1
Address Incrementing Interval every character clock every 2 character clocks every 4 character clocks every 2 character clocks
2
Horizontal Retrace Select This bit provides a method to effectively double the vertical resolution by allowing the vertical timing counter to be clocked by the horizontal retrace clock divided by 2 (usually, it would be undivided). 0: The vertical timing counter is clocked by the horizontal retrace clock. 1: The vertical timing counter is clocked by the horizontal retrace clock divided by 2. Select Row Scan Counter 0: A substitution takes place, whereby bit 14 of the 16-bit memory address generated by the memory address counter (after the stage at which these 16 bits may have already been shifted to accommodate word or doubleword addressing) is replaced with bit 1 of the row scan counter at a stage just before this address is presented to the frame buffer address decoder. 1: No substitution takes place. See the note at the end of this register description for an overview of the interactions between this and other bits.
1
0
Compatibility Mode Support 0: A substitution takes place, whereby bit 13 of the 16-bit memory address generated by the memory address counter (after the stage at which these 16 bits may have already been shifted to accommodate word or doubleword addressing) is replaced with bit 0 of the row scan counter at a stage just before this address is presented to the frame buffer address decoder. 1: No substitution takes place. See the note at the end of this register description for an overview of the interactions between this and other bits.
Note: The two tables that follow show the possible ways in which the address bits from the memory address counter can be shifted and/or reorganized before being presented to the frame buffer address decoder. First, the address bits generated by the memory address counter (MAOut0 to MAOut15) are reorganized, if needed, to accommodate byte, word, or doubleword modes. The resulting reorganized outputs (Reorg0 to Reorg15) may then also be further manipulated with the substitution of bits from the row scan counter (RSOut0 and RSOut1) before finally being presented to the input bits of the frame buffer address decoder (FBIn15-FBIn0).
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-29
Bits Generated by the Memory Address Counter (MAOut0 to MAOut15) Byte Mode CR14 bit 6=0 CR17 bit 6=1 CR17 bit 5=X MAOut0 MAOut1 MAOut2 MAOut3 MAOut4 MAOut5 MAOut6 MAOut7 MAOut8 MAOut9 MAOut10 MAOut11 MAOut12 MAOut13 MAOut14 MAOut15 OR Word Mode CR14 bit 6=0 CR17 bit 6=0 CR17 bit 5=1 MAOut15 MAOut0 MAOut1 MAOut2 MAOut3 MAOut4 MAOut5 MAOut6 MAOut7 MAOut8 MAOut9 MAOut10 MAOut11 MAOut12 MAOut13 MAOut14 OR Word Mode CR14 bit 6=0 CR17 bit 6=0 CR17 bit 5=0 MAOut13 MAOut0 MAOut1 MAOut2 MAOut3 MAOut4 MAOut5 MAOut6 MAOut7 MAOut8 MAOut9 MAOut10 MAOut11 MAOut12 MAOut13 MAOut14 OR Doubleword Mode CR14 bit 6=1 CR17 bit 6=X CR17 bit 5=X MAOut12 MAOut13 MAOut0 MAOut1 MAOut2 MAOut3 MAOut4 MAOut5 MAOut6 MAOut7 MAOut8 MAOut9 MAOut10 MAOut11 MAOut12 MAOut13 Resulting Reorganized Bits Reorg0 Reorg1 Reorg2 Reorg3 Reorg4 Reorg5 Reorg6 Reorg7 Reorg8 Reorg9 Reorg10 Reorg11 Reorg12 Reorg13 Reorg14 Reorg15 Bits Sent to the Frame Buffer Address Decoder FBIn0 FBIn1 FBIn2 FBIn3 FBIn4 FBIn5 FBIn6 FBIn7 FBIn8 FBIn9 FBIn10 FBIn11 FBIn12 FBIn13 FBIn14 FBIn15
CR17 bit 1=1 CR17 bit 0=1 Reorg0 Reorg1 Reorg2 Reorg3 Reorg4 Reorg5 Reorg6 Reorg7 Reorg8 Reorg9 Reorg10 Reorg11 Reorg12 Reorg13 Reorg14 Reorg15 OR
CR17 bit 1=1 CR17 bit 0=0 Reorg0 Reorg1 Reorg2 Reorg3 Reorg4 Reorg5 Reorg6 Reorg7 Reorg8 Reorg9 Reorg10 Reorg11 Reorg12 RSOut0 Reorg14 Reorg15 OR
CR17 bit 1=0 CR17 bit 0=1 Reorg0 Reorg1 Reorg2 Reorg3 Reorg4 Reorg5 Reorg6 Reorg7 Reorg8 Reorg9 Reorg10 Reorg11 Reorg12 Reorg13 RSOut1 Reorg15 OR
CR17 bit 1=0 CR17 bit 0=0 Reorg0 Reorg1 Reorg2 Reorg3 Reorg4 Reorg5 Reorg6 Reorg7 Reorg8 Reorg9 Reorg10 Reorg11 Reorg12 RSOut0 RSOut1 Reorg15
efmp69030 Databook
Revision 1.3 11/24/99
9-30
CRT Controller Registers
CR18
7 A B
Line Compare Register
6 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 18h shadowed for pipelines A and B
Line Compare Bits 7-0 Line Compare Bits 7-0
7-0
Line Compare Bits 7-0 This register provides the 8 least significant bits of a 10-bit value that specifies the scanline at which the memory address counter restarts at the value of 0. Bit 6 of the Maximum Scanline Register (CR09) supplies the most significant bit, and bit 4 of the Overflow Register (CR07) supplies the second most significant bit. Normally, this 10-bit value is set to specify a scanline after the last scanline of the active display area. When this 10-bit value is set to specify a scanline within the active display area, it causes that scanline and all subsequent scanlines in the active display area to display video data starting at the very first byte of the frame buffer. The result is what appears to be a screen split into a top and bottom part, with the image in the top part being repeated in the bottom part. When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low Register (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom parts displaying different data. The top part will display whatever data exists in the frame buffer starting at the address specified in the two start address registers (CR0C and CR0D), while the bottom part will display whatever data exists in the frame buffer starting at the first byte of the frame buffer.
CR22
7 A B
Memory Read Latch Data Register
6 5 4 3 2 1 0
read-only at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 22h shadowed for pipelines A and B
Memory Read Latch Data Memory Read Latch Data
7-0
Memory Read Latch Data This register provides the value currently stored in 1 of the 4 memory read latches. Bits 1 and 0 of the Read Map Select Register (GR04) select which of the 4 memory read latches may be read using this register.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-31
CR30
7 A B
Extended Vertical Total Register
6 Reserved Reserved 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 30h shadowed for pipelines A and B
Vertical Total Bits 11-8 Vertical Total Bits 11-8
7-4 3-0
Reserved These bits should always be written with the value of 0. Vertical Total Bits 11-8 The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes the scanlines both inside and outside of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical total is specified with a 10-bit value. The 8 least significant bits of the vertical total are supplied by bits 7-0 of the Vertical Total Register (CR06), and the 2 most significant bits are supplied by bits 5 and 0 of the Overflow Register (CR07). In standard VGA modes, these bits 3-0 of this register (CR30) are not used. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical total is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits 7-0 of the Vertical Total Register (CR06), and the 4 most significant bits are supplied by bits 3-0 of this register (CR30). This 10-bit or 12-bit value should be programmed to be equal to the total number of scanlines, minus 2.
efmp69030 Databook
Revision 1.3 11/24/99
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CRT Controller Registers
CR31
7 A B
Extended Vertical Display End Register
6 Reserved Reserved 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 31h shadowed for pipelines A and B
Vertical Sync Start Bits 11-8 Vertical Sync Start Bits 11-8
7-4 3-0
Reserved These bits should always be written with the value of 0. Vertical Display End Bits 11-8 The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last scanline within the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical display enable end is specified with a 10-bit value. The 8 least significant bits of the vertical display enable end are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the 2 most significant bits are supplied by bits 6 and 1 of the Overflow Register (CR07). In standard VGA modes bits 3-0 of CR31 are not used. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical display enable end is specified with a 12-bit value. The 8 least significant bits of the vertical display enable end are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the 4 most significant bits are supplied by these 4 bits of this register (CR31). This 10-bit or 12-bit value should be programmed to be equal to the number of the last scanline with in the active display area. Since the active display area always starts on the 0th scanline, this number should be equal to the total number of scanlines within the active display area, minus 1.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-33
CR32
7 A B
Extended Vertical Sync Start Register
6 Reserved Reserved 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 32h shadowed for pipelines A and B
Vertical Sync Start Bits 11-8 Vertical Sync Start Bits 11-8
7-4 3-0
Reserved These bits should always be written with the value of 0. Vertical Sync Start Bits 11-8 The vertical sync start is a 10-bit or 12-bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical sync start is specified with a 10-bit value. The 8 least significant bits of the vertical sync start are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the 2 most significant bits are supplied by bits 7 and 2 of the Overflow Register (CR07). In standard VGA modes, bits 3-0 of CR32 are not used. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical display end is specified with a 12-bit value. The 8 least significant bits of the vertical sync start are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the 4 most significant bits are supplied by bits 3-0 of this register (CR32). This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines from the beginning of the active display area to the start of the vertical sync pulse. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which the vertical sync pulse begins.
efmp69030 Databook
Revision 1.3 11/24/99
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CRT Controller Registers
CR33
7 A B
Extended Vertical Blanking Start Register
6 Reserved Reserved 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 33h shadowed for pipelines A and B
Vertical Blanking Start Bits 11-8 Vertical Blanking Start Bits 11-8
7-4 3-0
Reserved These bits should always be written with the value of 0. Vertical Blanking Start Bits 11-8 The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical blanking start is specified with a 10-bit value. The 8 least significant bits of the vertical blanking start are supplied by bits 7-0 of the Vertical Blanking Start Register (CR15), and the most and second-most significant bits are supplied by bit 5 of the Maximum Scanline Register (CR09) and bit 3 of the Overflow Register (CR07), respectively. In standard VGA modes, bits 3-0 if this register (CR33) are not used. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical blanking start is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits 7-0 of the Vertical Blanking Start Register (CR15), and the 4 most significant bits are supplied by bits 3-0 of this register (CR33). This 10-bit or 12-bit value should be programmed to be equal to the number of scan lines from the beginning of the active display area to the beginning of the blanking period. Since the active display area always starts on the 0th scanline, this number should be equal to the number of the scanline on which the vertical blanking period begins.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-35
CR38
7 A
Extended Horizontal Total Register
6 5 4 Reserved (0000:000) Reserved 3 2 1 0 Hor Total Bit 8 (0) Hor Total Bit 8 (0)
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 38h shadowed for pipelines A and B
B (0000:000)
7-1 0
Reserved These bits should always be written with the value of 0. Horizontal Total Bit 8 The horizontal total is an 8-bit or 9-bit value that specifies the total length of a scanline. This includes both the part of the scanline that is within the active display area and the part that is outside of it. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the horizontal total is specified with an 8-bit value. All 8 bits of the horizontal total are supplied by bits 7-0 of the Horizontal Total Register (CR00). In standard VGA modes, this bit is not used. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the horizontal total is specified with a 9-bit value. The 8 least significant bits of this value are supplied by bits 7-0 of the Horizontal Total Register (CR00), and the most significant bit is supplied by this bit of this register. This 8-bit or 9-bit value should be programmed to equal the total number of character clocks within the total length of a scanline minus 5. Note: For NTSC/PAL output support, CR79 can be used to add a programmable number of pixel clocks (as opposed to character clocks) to the horizontal total, permitting the horizontal total to be specified with greater precision.
efmp69030 Databook
Revision 1.3 11/24/99
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CRT Controller Registers
CR3C
7 A
Extended Horizontal Blanking End Register
6 5 4 3 Reserved (00:0000) Reserved (00:0000) 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 3Ch
Horizontal Blank End Bits 7 and 6 (00) Horizontal Blank End Bits 7 and 6 (00)
B
7-6
Horizontal Blanking End Bits 7and 6 The horizontal blanking end is a 6-bit or 8-bit value that specifies the end of the horizontal blanking period relative to its beginning. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the horizontal blanking end is specified with a 6-bit value. The 5 least significant bits of this value are supplied by bits 4-0 of the Horizontal Blanking End Register (CR03), and the most significant bit is supplied by bit 7 of the Horizontal Sync End Register (CR05). In standard VGA modes, this bit is not used. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the horizontal blanking end is specified with an 8-bit value. The 5 least significant bits of this value are supplied by bits 4-0 of the Horizontal Blanking End Register (CR03), the next most significant bit is supplied by bit 7 of the Horizontal Sync End Register (CR05), and both the most significant and 2nd most significant bits are supplied by bits 7 and 6, respectively, of this register. This 6-bit or 8-bit value should be programmed to be equal to the least significant 6 or 8 bits, respectively, of the result of adding the length of the blanking period in terms of character clocks to the value specified in the Horizontal Blanking Start Register (CR02).
5-0
Reserved These bits should always be written with the value of 0
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-37
CR40
7 A
Extended Start Address Register
6 5 Reserved (000) Reserved (000) 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 40h shadowed for pipelines A and B
Pipe A Strt Addr En (0) Pipe B Strt Addr En (0) Pipeline A Start Address Bits 19-16 (0000) Pipeline B Start Address Bits 19-16 (0000)
B
7
Extended Mode Start Address Enable This bit is used only in extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, to signal the hardware to update the start address. In extended modes, the start address is specified with a 20 bit value. These 20 bits, which are provided by the Start Address Low Register (CR0D), the Start Address High Register (CR0C) and bits 3-0 of this register, are double-buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance. To change the start address in extended modes, all three registers must be set for the new value, and then this bit of this register must be set to 1. Only if this is done, will the hardware update the start address on the next VSYNC. When this update has been performed, the hardware will set bit 7 of this register back to 0. Reserved Whenever this register is written to, these bits should be set to 0. Start Address Bits 19-16 The start address is a 16-bit or a 20-bit value that specifies the memory address offset from the beginning of the frame buffer at which the data to be shown in the active display area begins. In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the start address is specified with a 16-bit value. The eight bits of the Start Address High Register (CR0C) provide the eight most significant bits of this value, while the eight bits of the Start Address Low Register (CR0D) provide the eight least significant bits. In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the start address is specified with a 20-bit value. The four most significant bits are provided by bits 3-0 of this register, bits 15 through 8 of this value are provided by the Start Address High Register (CR0C), and the eight least significant bits are provided by the Start Address Low Register (CR0D). Note that in extended modes, these 20 bits are double-buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance. To change the start address in extended modes, all three registers must be set for the new value, and then bit 7 of this register must be set to 1. Only if this is done, will the hardware update the start address on the next VSYNC. When this update has been performed, the hardware will set bit 7 of this register back to 0.
6-4 3-0
efmp69030 Databook
Revision 1.3 11/24/99
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CRT Controller Registers
CR41
7 A B
Extended Span Register
6 Reserved Reserved 5 4 3 2 1 0
read/write at I/O address 3B5h/3D5h with 3B4h/3D4h set to index 41 shadowed for pipelines A and B
Offset Bits 11-8 Offset Bits 11-8
7-4 3-0
Reserved Whenever this register is written to, these bits should be set to 0. Offset Bits 11-8 The offset is an 8-bit or 12-bit value describing the number of words or doublewords of frame buffer memory occupied by each horizontal row of characters. Whether this value is interpreted as the number of words or doublewords is determined by the settings of the bits in the Clocking Mode Register (SR01). In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the offset is described with an 8-bit value, all the bits of which are provided by the Offset Register (CR13). In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the offset is described with a 12-bit value. The four most significant bits of this value are provided by bits 3-0 of this register, and the eight least significant bits are provided by the Offset Register (CR13). This 8-bit or 12-bit value should be programmed to be equal to either the number of words or doublewords (depending on the setting of the bits in the Clocking Mode Register, SR01) of frame buffer memory that is occupied by each horizontal row of characters.
CR70
7 A B
Interlace Control Register
6 5 4 3 CRT Half-Line Value CRT Half-Line Value 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 70h shadowed for pipelines A and B
Interlace Enable Interlace Enable
7
Interlace Enable 0: Selects non-interlaced CRT output. This is the default after reset. 1: Selects interlaced CRT output. CRT Half-Line Value When interlaced CRT output has been selected, these 7 bits specify the position along the length of a scan line at which the half-line vertical sync pulse occurs for the odd frame. This half-line vertical sync pulse begins at a position between two horizontal sync pulses on the last scanline, rather than coincident with the beginning of a horizontal sync pulse at the end of a scanline.
6-0
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-39
CR71
7 A B
NTSC/PAL Video Output Control Register
6 Pedestal Enable 5 Blanking Delay Ctrl 4 reserved 3 2 1 Composite Sync Pixel Clk Delay 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 71h shadowed only for pipeline B
NTSC/ PAL Sel
Composite Sync Character Clk Delay
7
NTSC/PAL Select 0: Selects NTSC-formatted video output. 1: Selects PAL-formatted video output. Pedestal Enable 0: Disables the provision of an additional voltage pedestal on red, green and blue analog output lines during the active video portions of each horizontal line. 1: Enables the provision of an additional voltage pedestal on the red, green, and blue analog output lines during the active video portions of each horizontal line. Blanking Delay Control 0: Blanking period is not delayed on odd frames. 1: Blanking period is delayed by half a scanline on odd frames. Composite Sync Character Clock Delay These 2 bits specify the number of character clocks (from 0 to 3) by which the composite sync may be delayed. Composite Sync Pixel Clock Delay These 3 bits specify the number of pixel clocks (from 0 to 7) by which the composite sync may be delayed.
6
5
4-3
2-0
efmp69030 Databook
Revision 1.3 11/24/99
9-40
CRT Controller Registers
CR72
7 A B
NTSC/PAL Horizontal Serration 1 Start Register
6 5 4 reserved Horizontal Serration 1 Start 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 72h shadowed only for pipeline B
7-0
Horizontal Serration 1 Start These 8 bits specify the start position along the length of a scanline of the first horizontal serration pulse for composite sync generation.
CR73
7 A B
NTSC/PAL Horizontal Serration 2 Start Register
6 5 4 reserved Horizontal Serration 2 Start 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 73h shadowed only for pipeline B
7-0
Horizontal Serration 2 Start These 8 bits specify the start position along the length of a scanline of the second horizontal serration pulse for composite sync generation.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-41
CR74
7 A B
NTSC/PAL Horizontal Pulse Width Register
6 Reserved 5 Round Off 4 reserved NTSC/PAL Horizontal Equalization Pulse Width 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 74h shadowed only for pipeline B
7-6 5
Reserved NTSC/PAL Horizontal Pulse Width Round Off Control 0: Enables the generation of horizontal equalization pulses with a width that is approximately equal to half the width of the horizontal sync pulse. The actual width is determined using bits 4-0 of this register. 1: Disables the generation of horizontal equalization pulses. NTSC/PAL Horizontal Equalization Pulse Width These 5 bits specify the pulse width of the horizontal equalization pulse used to generate the NTSC/PAL-compliant composite sync. Normally, the width of this horizontal equalization pulse is approximately half the width of the horizontal sync pulse. These 5 bits should be programmed with a value equal to the actual pulse width, subtracted by 1. The width of the actual equalization pulse can be calculated as follows: equalization pulse width - 1 = (CR74[4:0] - CR74[5]) / 2
4-0
efmp69030 Databook
Revision 1.3 11/24/99
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CRT Controller Registers
CR75
7 A B
NTSC/PAL Filtering Burst Read Length Register
6 5 4 reserved Reserved (Writable) (xxxx) Memory Burst Read Length (xxxx) 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 75h shadowed only for pipeline B
7-4 3-0
Reserved These bits should always be written with the value of 0. Memory Burst Access Segment Length The flicker reduction filtering processes are performed on pixel data as it is sequentially read from the frame buffer to be displayed. These filtering processes involve the averaging of current pixel data that is about to be displayed with data for adjacent pixels. Depending upon which filtering processes are selected, accesses to the frame buffer can become nonsequential. To optimize the use of the frame buffer, burst accesses of one or more quadwords are performed to read this data. These 4 bits provide a means of adjusting how many quadwords of pixel data are read from the frame buffer in each burst access.
CR76
7 A B
NTSC/PAL Filtering Burst Read Quantity Register
6 5 4 reserved Memory Burst Access Segments Per Scanline (xxxx:xxxx) 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 76h shadowed only for pipeline B
7-0
Memory Burst Access Segments Per Scanline These 8 bits specify the number of burst reads required to supply both current pixel data and pixel data from adjacent pixels for each scanline's worth of displayable pixel data. Refer to the NTSC/PAL Filtering Burst Read Length Register (CR75) for an explanation of these burst reads.
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-43
CR77
7 A B
NTSC/PAL Filtering Control Register
6 5 4 reserved 3 2 1 Clk Doubling Enable (0) 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 77h shadowed only for pipeline B
Text Mode Line Halving (0)
Reserved (Writable) (000)
Hor. Filter Enable (0)
Ver. Filter Enable (0)
Filtering Enable (0)
7
VGA Text Mode Scanline Halving 0: Disables VGA text mode scanline halving. 1: Enables VGA text mode scanline halving, where the setting carried in the Maximum Scanline Register (CR09) and that carried by bits 4-0 of the Text Cursor End Register (CR0B) are halved. This is done to cut the number of scanlines actually sent to the display from VGA standard quantities (such as 400) down to quantities that are more manageable for televisions (such as 200) without actually programming CR09 and bits 4-0 of CR0B with values that are different from VGA standards. This function is meant to be used in conjunction with character fonts that are only half as high as those normally used in VGA text modes. Reserved (Writable) These bits should always be written with the value of 0. Horizontal Flicker Reduction Filtering Enable Note: Bits 1 and 0 of this register must both be set to 1 in order to enable the flicker reduction filtering hardware, before horizontal flicker reduction filtering can be enabled through this bit. 0: Disables horizontal flicker reduction filtering 1: Enables horizontal flicker reduction filtering where the current pixel is averaged with the pixels immediately to the left and right on the same scanline. This averaging process uses weighted averaging. The current pixel's value is divided by 2, the values of each of the two adjacent pixels is divided by 4, and the resulting three values are added to create the value that is displayed. Vertical Flicker Reduction Filtering Enable Note: Bits 1 and 0 of this register must both be set to 1 in order to enable the flicker reduction filtering hardware, before vertical flicker reduction filtering can be enabled through this bit. 0: Disables vertical flicker reduction filtering 1: Enables vertical flicker reduction filtering where the pixels of the current scanline are averaged with the pixels of the next scanline as the pixels of the current scanline are being displayed. Internal Clock Doubling Enable 0: One of the internal clocks used by the graphics controller remains at normal clock rates. 1: One of the internal clocks used by the graphics controller is doubled in frequency. Flicker Reduction Filtering Enable Note: Bit 1 of this register should be set to enable the doubling of an internal clock, before the use of the flicker reduction hardware is enabled by setting this bit to 1. 0: Disables all flicker reduction filter hardware. 1: Enables the use of the flicker reduction filter hardware.
6-4 3
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
9-44
CRT Controller Registers
CR78
7 A B
NTSC/PAL Vertical Reduction Register
6 Reserved (0) 5 Reserved (0) 4 reserved 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 78h shadowed only for pipeline B
Vertical Redux En (0)
Vertical Reduction Line Dropping Interval (0:0000)
7
Vertical Reduction Enable 0: Vertical reduction is disabled. This is the default after reset. 1: Vertical reduction is enabled Reserved These bits always return the value of 0 when read. Vertical Reduction Line Dropping Interval When bit 7 of this register is set to 1, these 5 bits specify the number of scanlines remaining (those which will be drawn on the display) between each of the scanlines that are to be dropped (those which will NOT be drawn on the display).
Bit 43210 00000 00001 00010 to 11111 Number of Scanlines Remaining Between Dropped Scanlines Reserved Reserved 2 to 31
6-5 4-0
efmp69030 Databook
Revision 1.3 11/24/99
CRT Controller Registers
9-45
CR79
7 A
NTSC/PAL Horizontal Total Fine Adjust Register
6 5 Reserved (Writable) 4 reserved NTSC/PAL Horizontal Total Fine Adjust (000) 3 2 1 0
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 79h shadowed only for pipeline B
B (0000:0)
7-3 2-0
Reserved Horizontal Total Fine Adjust These 3 bits can be use to specify a number of pixel clocks to be added to the horizontal total specified either by the Horizontal Total Register (CR00) alone in VGA standard modes, or by the Horizontal Total Register (CR00) in conjunction with the Extended Horizontal Total Register (CR38) for extended modes -- both of which specify their respective portions of the horizontal total in units of character clocks. The pixel clock granularity of these 3 bits permit the horizontal total to be specified with greater precision than is possible with character clocks, alone.
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CRT Controller Registers
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Sequencer Registers
10-1
Chapter 10 Sequencer Registers
Introduction
The Sequencer Registers are accessed by writing the index of the desired register into the VGA Sequencer Index Register (SRX) at I/O address 3C4, and then accessing the desired register through the data port for the sequencer registers at I/O address 3C5. Table 10-1:
Name SR00 SR01 SR02 SR03 SR04 SR07 Reset Register Clocking Mode Register Plane Mask Register Character Map Select Register Memory Mode Register Horizontal Character Counter Reset Register
Sequencer Registers
Function Access (via 3C5) read/write read/write read/write read/write read/write read/write Index Value In 3C4 (SRX) 00 01 02 03 04 07
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Sequencer Registers
SRX
7
Sequencer Index Register
6 5 Reserved 4 3 2 1 Sequencer Register Index 0
read/write at I/O address 3C4h This register is cleared to 00h by reset.
7-3 2-0
Reserved Sequencer Register Index These three bits are used to select any one of the sequencer registers, SR00 through SR07, to be accessed via the data port at I/O location 3C5. Note: SR02 is referred to in the VGA standard as the Map Mask Register. However, the word "map" is used with multiple meanings in the VGA standard and was therefore deemed too confusing, hence the reason for calling it the Plane Mask Register. Note: SR07 is a standard VGA register that was not documented by IBM. It is not a Intel extension.
SR00
7 A & B
Reset Register
6 5 Reserved 4 3 2 1 0
read/write at I/O address 3C5h with index at address 3C4h set to 00h shared by both pipelines A and B
Sync Reset Async Reset
7-2 1
Reserved Synchronous Reset Setting this bit to 0 commands the sequencer to perform a synchronous clear and then halt. The sequencer should be reset via this bit before changing the Clocking Mode Register (SR01) if the memory contents are to be preserved. However, leaving this bit set to 0 for longer than a few tenths of a microsecond can still cause data loss in the frame buffer. No register settings are changed by performing this type of reset. 0: Forces synchronous reset and halt 1: Permits normal operation Asynchronous Reset Setting this bit to 0 commands the sequencer to perform a clear and then halt. Resetting the sequencer via this bit can cause data loss in the frame buffer. No register settings are changed by performing this type of reset. 0: Forces asynchronous reset 1: Permits normal operation
0
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10-3
SR01
7 A B
Clocking Mode Register
6 Reserved Reserved 5 Screen Off Screen Off 4 Shift 4 Shift 4 3 Dot Clock Divide Dot Clock Divide 2 Shift Load Shift Load 1 Reserved Reserved 0 8/9 Dot Clocks 8/9 Dot Clocks
read/write at I/O address 3C5h with index at address 3C4h set to 01h shadowed for pipelines A and B
7-6 5
Reserved Screen Off 0: Permits normal operation 1: Disables all graphics output except for video playback windows and turns off the picturegenerating logic allowing the full memory bandwidth to be available for both host CPU accesses and accesses by the multimedia engine for video capture and playback functions. Synchronization pulses to the display, however, are maintained. Setting this bit to 1 can be used as a way to more rapidly update the frame buffer. Shift 4 0: Causes the video data shift registers to be loaded every 1 or 2 character clock cycles, depending on bit 2 of this register. 1: Causes the video data shift registers to be loaded every 4 character clock cycles.
4
3
Dot Clock Divide Setting this bit to 1 divides the dot clock by two and stretches all timing periods. This bit is used in standard VGA 40-column text modes to stretch timings to create horizontal resolutions of either 320 or 360 pixels as opposed to 640 or 720 pixels, normally used in standard VGA 80-column text modes. 0: Pixel clock is left unaltered. 1: Pixel clock is divided by 2. Shift Load This bit is ignored if bit 4 of this register is set to 1. 0: Causes the video data shift registers to be loaded on every character clock, if bit 4 of this register is set to 0. 1: Causes the video data shift registers to be loaded every 2 character clocks, provided that bit 4 of this register is set to 0. Reserved 8/9 Dot Clocks 0: Selects 9 dot clocks (9 horizontal pixels) per character in text modes with a horizontal resolution of 720 pixels 1: Selects 8 dot clocks (8 horizontal pixels) per character in text modes with a horizontal resolution of 640 pixels
2
1 0
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10-4
Sequencer Registers
SR02
7 A & B
Plane Mask Register
6 Reserved 5 4 3 Memory Plane 3 2 Memory Plane 2 1 Memory Plane 1 0 Memory Plane 0
read/write at I/O address 3C5h with index at address 3C4h set to 02h shared by both pipelines A and B
Note: This register is referred to in the VGA standard as the Map Mask Register. However, the word "map" is used with multiple meanings in the VGA standard and was, therefore, deemed too confusing, hence the reason for calling it the Plane Mask Register. 7-4 3-0 Reserved Memory Plane 3 through Memory Plane 0 These four bits of this register control processor write access to the four memory maps: 0: Disables CPU write access to the given memory plane 1: Enables CPU write access to the given memory plane In both the Odd/Even Mode and the Chain 4 Mode, these bits still control access to the corresponding color plane.
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Sequencer Registers
10-5
SR03
7 A & B
Character Map Select Register
6 Reserved 5 4 3 2 1 0
read/write at I/O address 3C5h with index at address 3C4h set to 03h shared by both pipelines A and B
Char Map A Char Map B Select (bit 0) Select (bit 0) Character Map A Select (bits 2 and 1) Character Map B Select (bits 2 and 1)
Note: In text modes, bit 3 of the video data's attribute byte normally controls the foreground intensity. This bit may be redefined to control switching between character sets. This latter function is enabled whenever there is a difference in the values of the Character Font Select A and the Character Font Select B bits. If the two values are the same, the character select function is disabled and attribute bit 3 controls the foreground intensity. 7-6 5, 3-2 Reserved Character Map Select Bits for Character Map A These three bits are used to select the character map (character generator tables) to be used as the secondary character set (font). Note that the numbering of the maps is not sequential.
Bit 32 00 00 01 01 10 10 11 11 Bit 5 0 1 0 1 0 1 0 1 Map Number 0 4 1 5 2 6 3 7 Table Location 1st 8KB of plane 2 at offset 0 2nd 8KB of plane 2 at offset 8K 3rd 8KB of plane 2 at offset 16K 4th 8KB of plane 2 at offset 24K 5th 8KB of plane 2 at offset 32K 6th 8KB of plane 2 at offset 40K 7th 8KB of plane 2 at offset 48K 8th 8KB of plane 2 at offset 56K
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10-6 4, 1-0
Sequencer Registers Character Map Select Bits for Character Map B These three bits are used to select the character map (character generator tables) to be used as the primary character set (font). Note that the numbering of the maps is not sequential.
Bit 10 00 00 01 01 10 10 11 11 Bit 4 0 1 0 1 0 1 0 1 Map Number 0 4 1 5 2 6 3 7 Table Location 1st 8KB of plane 2 at offset 0 2nd 8KB of plane 2 at offset 8K 3rd 8KB of plane 2 at offset 16K 4th 8KB of plane 2 at offset 24K 5th 8KB of plane 2 at offset 32K 6th 8KB of plane 2 at offset 40K 7th 8KB of plane 2 at offset 48K 8th 8KB of plane 2 at offset 56K
Note: Bit 1 of the Memory Mode Register (SR04) must be set to 1 for the character font select function of this register to be active. Otherwise, only character maps 0 and 4 are available.
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10-7
SR04
7 A & B
Memory Mode Register
6 Reserved 5 4 3 Chain 4 2 Odd/ Even 1 Extended Memory 0 Reserved
read/write at I/O address 3C5h with index at address 3C4h set to 04h shared by both pipelines A and B
7-4 3
Reserved Chain 4 Mode 0: The manner in which the frame buffer memory is mapped is determined by the setting of bit 2 of this register. 1: The frame buffer memory is mapped in such a way that the function of address bits 0 and 1 are altered so that they select planes 0 through 3. The selections made by this bit affect both CPU read and write accesses to the frame buffer. Odd/Even Mode 0: The frame buffer is mapped so that address bit 0 is used to select between sets of planes such that even addresses select memory planes 0 and 2 and odd addresses select memory planes 1 and 3. 1: Addresses sequentially access data within a bit map, and the choice of which map is accessed is made according to the value of the Plane Mask Register (SR02). Note: Bit 3 of this register must be set to 0 for this bit to be effective. The selections made by this bit affect only CPU writes to the frame buffer. Note: This works in a way that is the inverse of (and is normally set to be the opposite of) bit 2 of the Memory Mode Register (SR04).
2
1
Extended Memory Enable 0: Disable CPU accesses to more than the first 64KB of VGA standard memory. 1: Enable CPU accesses to the rest of the 256KB total VGA memory beyond the first 64KB. This bit must be set to 1 to enable the selection and use of character maps in plane 2 via the Character Map Select Register (SR03). Reserved
0
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10-8
Sequencer Registers
SR07
7 A & B
Horizontal Character Counter Reset Register
6 5 4 3 2 1 0
read/write at I/O address 3C5h with index at address 3C4h set to index 07h shared by both pipelines A and B
Horizontal Character Counter Reset
Writing this register with any data will cause the horizontal character counter to be held in reset (the character counter output will remain 0) until a write occurs to any other sequencer register location with SRX set to an index of 0 through 6. The vertical line counter is clocked by a signal derived from the horizontal display enable (which does not occur if the horizontal counter is held in reset). Therefore, if a write occurs to this register occurs during the vertical retrace interval, both the horizontal and vertical counters will be set to 0. A write to any other sequencer register location (with SRX set to an index of 0 through 6) may then be used to start both counters with reasonable synchronization to an external event via software control. This is a standard VGA register which was not documented by IBM.
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Graphics Controller Registers
11-1
Chapter 11 Graphics Controller Registers
Introduction
The Graphics Controller Registers are accessed by writing the index of the desired register into the VGA Graphics Controller Index Register (GRX) at I/O address 3CE, then accessing the desired register through the data port for the graphics controller registers located at I/O address 3CF. Table 11-1: Name GR00 GR01 GR02 GR03 GR04 GR05 GR06 GR07 GR08 Graphics Controller Registers Function Set/Reset Register Enable Set/Reset Register Color Compare Register Data Rotate Register Read Map Select Register Graphics Mode Register Miscellaneous Register Color Don't Care Register Bit Mask Register
Access (via 3CF) read/write read/write read/write read/write read/write read/write read/write read/write read/write
Index Value In 3CE (GRX) 00h 01h 02h 03h 04h 05h 06h 07h 08h
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Graphics Controller Registers
GRX
7
Graphics Controller Index Register
6 Reserved 5 4 3 2 1 0
read/write at I/O address 3CEh this register is cleared to 00h by reset.
Graphics Controller Register Index
7-4 3-0
Reserved Graphics Controller Register Index These four bits are used to select any one of the graphics controller registers, GR00 through GR08, to be accessed via the data port at I/O location 3CF.
GR00
7 A & B
Set/Reset Register
6 Reserved 5 4 3 Set/Reset Plane 3 2 Set/Reset Plane 2 1 Set/Reset Plane 1 0 Set/Reset Plane 0
read/write at I/O address 3CFh with index at address 3CEh set to 00h shared by both pipelines A and B
7-4 3-0
Reserved Set/Reset Plane 3 through Set/Reset Plane 0 When the Write Mode bits (bits 0 and 1) of the Graphics Mode Register (GR05) are set to select Write Mode 0, all 8 bits of each byte of each memory plane are set to either 1 or 0 as specified in the corresponding bit in this register if the corresponding bit in the Enable Set/Reset Register (GR01) is set to 1. When the Write Mode bits (bits 0 and 1) of the Graphics Mode Register (GR05) are set to select Write Mode 3, all CPU data written to the frame buffer is rotated, then logically ANDed with the contents of the Bit Mask Register (GR08) and then treated as the addressed data's bit mask, while value of these four bits of this register are treated as the color value.
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11-3
GR01
7 A & B
Enable Set/Reset Register
6 Reserved 5 4 3 Enbl Set/ Reset Pln 3 2 Enbl Set/ Reset Pln 2 1 Enbl Set/ Reset Pln 1 0 Enbl Set/ Reset Pln 0
read/write at I/O address 3CFh with index at address 3CEh set to 01h shared by both pipelines A and B
7-4 3-0
Reserved Enable Set/Reset Plane 3 through Enable Set/Reset Plane 0 0: The corresponding memory plane can be read from or written to by the CPU without any special bitwise operations taking place. 1: The corresponding memory plane is set to 0 or 1 as specified in the Set/Reset Register (GR00). This register works in conjunction with the Set/Reset Register (GR00). The Write Mode bits (bits 0 and 1) must be set for Write Mode 0 for this register to have any effect.
GR02
7 A & B
Color Compare Register
6 Reserved 5 4 3 2 1 0 Color Comp Plane 0
read/write at I/O address 3CFh with index at address 3CEh set to 02h shared by both pipelines A and B
Color Comp Color Comp Color Comp Plane 3 Plane 2 Plane 1
7-4 3-0
Reserved Color Compare Plane 3 through Color Compare Plane 0 When the Read Mode bit (bit 3) of the Graphics Mode Register (GR05) is set to select Read Mode 1, all 8 bits of each byte of each of the 4 memory planes of the frame buffer corresponding to the address from which a CPU read access is being performed are compared to the corresponding bits in this register (if the corresponding bit in the Color Don't Care Register (GR07) is set to 1). The value that the CPU receives from the read access is an 8-bit value that shows the result of this comparison, wherein a value of 1 in a given bit position indicates that all of the corresponding bits in the bytes across all of the memory planes that were included in the comparison had the same value as their memory plane's respective bits in this register.
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11-4
Graphics Controller Registers
GR03
7 A & B
Data Rotate Register
6 Reserved 5 4 3 2 1 Rotate Count 0
read/write at I/O address 3CFh with index at address 3CEh set to 03h shared by both pipelines A and B
Function Select
7-5 4-3
Reserved Function Select These bits specify the logical function (if any) to be performed on data that is meant to be written to the frame buffer (using the contents of the memory read latch) just before it is actually stored in the frame buffer at the intended address location.
Bit 45 00 01 10 11
Result Data being written to the frame buffer remains unchanged, and is simply stored in the frame buffer. Data being written to the frame buffer is logically ANDed with the data in the memory read latch before it is actually stored in the frame buffer. Data being written to the frame buffer is logically ORed with the data in the memory read latch before it is actually stored in the frame buffer. Data being written to the frame buffer is logically XORed with the data in the memory read latch before it is actually stored in the frame buffer.
2-0
Rotate Count These bits specify the number of bits to the right to rotate any data that is meant to be written to the frame buffer just before it is actually stored in the frame buffer at the intended address location.
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11-5
GR04
7 A & B
Read Plane Select Register
6 5 Reserved 4 3 2 1 0
read/write at I/O address 3CFh with index at address 3CEh set to 04h shared by both pipelines A and B
Read Plane Select
7-2 1-0
Reserved Read Plane Select These two bits select the memory plane from which the CPU reads data in Read Mode 0. In Odd/Even Mode, bit 0 of this register is ignored. In Chain 4 Mode, both bits 1 and 0 of this register are ignored. The four memory planes are selected as follows:
Bits 10 00 01 10 11
Plane Selected Plane 0 Plane 1 Plane 2 Plane 3
These two bits also select which of the four memory read latches may be read via the Memory Read Latch Data Register (CR22). The choice of memory read latch corresponds to the choice of plane specified in the table above. The Memory Read Latch Data register and this additional function served by 2 bits are features of the VGA standard that were never documented by IBM.
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11-6
Graphics Controller Registers
GR05
7 A & B
Graphics Mode Register
6 5 4 Odd/ Even 3 Read Mode 2 Reserved 1 Write Mode 0
read/write at I/O address 3CFh with index at address 3CEh set to 05h shared by both pipelines A and B
Reserved
Shift Register Control
7 6-5
Reserved Shift Register Control In standard VGA modes, pixel data is transferred from the 4 graphics memory planes to the palette via a set of 4 serial output bits. These 2 bits of this register control the format in which data in the 4 memory planes is serialized for these transfers to the palette. 0, 0: One bit of data at a time from parallel bytes in each of the 4 memory planes is transferred to the palette via the 4 serial output bits, with 1 of each of the serial output bits corresponding to a memory plane. This provides a 4-bit value on each transfer for 1 pixel, making possible a choice of 1 of 16 colors per pixel.
Serial Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer Bit 3 Bit 2 Bit 1 Bit 0 plane 3 bit 7 plane 2 bit 7 plane 1 bit 7 plane 0 bit 7 plane 3 bit 6 plane 2 bit 6 plane 1 bit 6 plane 0 bit 6 plane 3 plane 3 plane 3 plane 3 plane 3 plane 3 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 plane 2 plane 2 plane 2 plane 2 plane 2 plane 2 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 plane 1 plane 1 plane 1 plane 1 plane 1 plane 1 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 plane 0 plane 0 plane 0 plane 0 plane 0 plane 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0, 1: Two bits of data at a time from parallel bytes in each of the 4 memory planes are transferred to the palette in a pattern that alternates per byte between memory planes 0 and 2, and memory planes 1 and 3. First the even-numbered and odd-numbered bits of a byte in memory plane 0 are transferred via serial output bits 0 and 1, respectively, while the even-numbered and odd-numbered bits of a byte in memory plane 2 are transferred via serial output bits 2 and 3. Next, the even-numbered and odd-numbered bits of a byte in memory plane 1 are transferred via serial output bits 0 and 1, respectively, while the evennumbered and odd-numbered bits of memory plane 3 are transferred via serial out bits 1 and 3. This provides a pair of 2-bit values (one 2-bit value for each of 2 pixels) on each transfer, making possible a choice of 1 of 4 colors per pixel.
Serial Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer Bit 3 Bit 2 Bit 1 Bit 0 plane 2 bit 7 plane 2 bit 6 plane 0 bit 7 plane 0 bit 6 plane 2 bit 5 plane 2 bit 4 plane 0 bit 5 plane 0 bit 4 plane 2 bit 3 plane 2 bit 2 plane 0 bit 3 plane 0 bit 2 plane 2 bit 1 plane 2 bit 0 plane 0 bit 1 plane 0 bit 0 plane 3 bit 7 plane 3 bit 6 plane 1 bit 7 plane 1 bit 6 plane 3 bit 5 plane 3 bit 4 plane 1 bit 5 plane 1 bit 4 plane 3 bit 3 plane 3 bit 2 plane 1 bit 3 plane 1 bit 2 plane 3 bit 1 plane 3 bit 0 plane 1 bit 1 plane 1 bit 0
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Graphics Controller Registers This alternating pattern is meant to accommodate the use of the Odd/Even mode of organizing the 4 memory planes, which is used by standard VGA modes 2h and 3h.
11-7
1, x: Four bits of data at a time from parallel bytes in each of the 4 memory planes are transferred to the palette in a pattern that iterates per byte through memory planes 0 through 3. First the 4 most significant bits of a byte in memory plane 0 are transferred via the 4 serial output bits, followed by the 4 least significant bits of the same byte. Next, the same transfers occur from the parallel byte in memory planes 1, 2 and lastly, 3. Each transfer provides either the upper or lower half of an 8 bit value for the color for each pixel, making possible a choice of 1 of 256 colors per pixel.
Serial Out 1st Xfer Bit 3 Bit 2 Bit 1 Bit 0
2nd Xfer
3rd Xfer
4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer
plane 0 plane 0 plane 1 plane 1 plane 2 plane 2 plane 3 plane 3 bit 7 bit 3 bit 7 bit 3 bit 7 bit 3 bit 7 bit 3 plane 0 plane 0 plane 1 plane 1 plane 2 plane 2 plane 3 plane 3 bit 6 bit 2 bit 6 bit 2 bit 6 bit 2 bit 6 bit 2 plane 0 plane 0 plane 1 plane 1 plane 2 plane 2 plane 3 plane 3 bit 5 bit 1 bit 5 bit 1 bit 5 bit 1 bit 5 bit 1 plane 0 plane 0 plane 1 plane 1 plane 2 plane 2 plane 3 plane 3 bit 4 bit 0 bit 4 bit 0 bit 4 bit 0 bit 4 bit 0
This pattern is meant to accommodate mode 13h, a standard VGA 256-color graphics mode. 4 Odd/Even Mode 0: Addresses sequentially access data within a bit map. The choice of which map is accessed is made according to the value of the Plane Mask Register (SR02). 1: The frame buffer is mapped so that address bit 0 is used to select between sets of planes such that even addresses select memory planes 0 and 2 and odd addresses select memory planes 1 and 3. Note: This works in a way that is the inverse of (and is normally set to be the opposite of) bit 2 of the Memory Mode Register (SR04).
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11-8 3
Graphics Controller Registers Read Mode 0: During a CPU read from the frame buffer, the value returned to the CPU is data from the memory plane selected by bits 1 and 0 of the Read Plane Select Register (GR04). 1: During a CPU read from the frame buffer, all 8 bits of the byte in each of the 4 memory planes corresponding to the address from which a CPU read access is being performed are compared to the corresponding bits in this register (if the corresponding bit in the Color Don't Care Register (GR07) is set to 1). The value that the CPU receives from the read access is an 8-bit value that shows the result of this comparison, wherein value of 1 in a given bit position indicates that all of the corresponding bits in the bytes across all 4 of the memory planes that were included in the comparison had the same value as their memory plane's respective bits in this register. Reserved Write Mode 0, 0: Write Mode 0 -- During a CPU write to the frame buffer, the addressed byte in each of the 4 memory planes is written with the CPU write data after it has been rotated by the number of counts specified in the Data Rotate Register (GR03). If, however, the bit(s) in the Enable Set/Reset Register (GR01) corresponding to one or more of the memory planes is set to 1, then those memory planes will be written to with the data stored in the corresponding bits in the Set/Reset Register (GR00). 0, 1: Write Mode 1 -- During a CPU write to the frame buffer, the addressed byte in each of the 4 memory planes is written to with the data stored in the memory read latches (the memory read latches stores an unaltered copy of the data last read from any location in the frame buffer). 1, 0: Write Mode 2 -- During a CPU write to the frame buffer, the least significant 4 data bits of the CPU write data are treated as the color value for the pixels in the addressed byte in all 4 memory planes. The 8 bits of the Bit Mask Register (GR08) are used to selectively enable or disable the ability to write to the corresponding bit in each of the 4 memory planes that correspond to a given pixel. A setting of 0 in a bit in the Bit Mask Register at a given bit position causes the bits in the corresponding bit positions in the addressed byte in all 4 memory planes to be written with value of their counterparts in the memory read latches. A setting of 1 in a Bit Mask Register at a given bit position causes the bits in the corresponding bit positions in the addressed byte in all 4 memory planes to be written with the 4 bits taken from the CPU write data to thereby cause the pixel corresponding to these bits to be set to the color value. 1, 1: Write Mode 3 -- During a CPU write to the frame buffer, the CPU write data is logically ANDed with the contents of the Bit Mask Register (GR08). The result of this ANDing is treated as the bit mask used in writing the contents of the Set/Reset Register (GR00) are written to addressed byte in all 4 memory planes.
2 1-0
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11-9
GR06
7 A & B
Miscellaneous Register
6 Reserved 5 4 3 2 1 Chain Odd/ Even 0 Graphics / Text Mode
read/write at I/O address 3CFh with index at address 3CEh set to 06h shared by both pipelines A and B (except bit 0, which is shadowed for pipelines A and B)
Memory Map Mode
7-4 3-2
Reserved Memory Map Mode These 2 bits control the mapping of the frame buffer into the CPU address space as follows:
Bits 32 00 01 10 11
Frame Buffer Address Range A0000h - BFFFFh A0000h - AFFFFh B0000h - B7FFFh B8000h - BFFFFh
Note: This function is both in standard VGA modes and in extended modes that do not provide linear frame buffer access. 1 Chain Odd/Even This bit provides the ability to alter the interpretation of address bit A0, so that it may be used in selecting between the odd-numbered memory planes (planes 1 and 3) and the even-numbered memory planes (planes 0 and 2). 0: A0 functions normally. 1: A0 is switched with a high order address bit, in terms of how it is used in address decoding. The result is that A0 is used to determine which memory plane is being accessed: A0 = 0: planes 0 and 2 A0 = 1: planes 1 and 3 Graphics/Text Mode (shadowed) 0: Selects text mode. 1: Selects graphics mode.
0
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Graphics Controller Registers
GR07
7 A & B
Color Don't Care Register
6 Reserved 5 4 3 Ignore Color Plane 3 2 Ignore Color Plane 2 1 Ignore Color Plane 1 0 Ignore Color Plane 0
read/write at I/O address 3CFh with index at address 3CEh set to 07h shared by both pipelines A and B
7-4 3-0
Reserved Ignore Color Plane 3 through Ignore Color Plane 0 0: The corresponding bit in the Color Compare Register (GR02) will not be included in color comparisons. 1: The corresponding bit in the Color Compare Register (GR02) is used in color comparisons. Note: These bits have effect only when bit 3 of the Graphics Mode Register (GR05) is set to 1 to select read mode 1.
GR08
7 A & B
Bit Mask Register
6 5 4 Bit Mask 3 2 1 0
read/write at I/O address 3CFh with index at address 3CEh set to 08h shared by both pipelines A and B
7-0
Bit Mask 0: The corresponding bit in each of the 4 memory planes is written to with the corresponding bit in the memory read latches. 1: Manipulation of the corresponding bit in each of the 4 memory planes via other mechanisms is enabled. Note: This bit mask applies to any writes to the addressed byte of any or all of the 4 memory planes simultaneously. Note: This bit mask is applicable to any data written into the frame buffer by the CPU, including data that is also subject to rotation, logical functions (AND, OR, XOR), and Set/ Reset. To perform a proper read-modify-write cycle into the frame buffer, each byte must first be read from the frame buffer by the CPU (and this will cause it to be stored in the memory read latches), this Bit Mask Register must be set and the new data then written into the frame buffer by the CPU.
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Attribute Controller Registers
12-1
Chapter 12 Attribute Controller Registers
Introduction
Unlike the other sets of indexed registers, the Attribute Controller Registers are not accessed through a scheme employing entirely separate index and data ports. I/O address 3C0h is used both as the read and write for the index register, and as the write address for the data port. I/O address 3C1h is the read address for the data port. Table 12-1:
Name AR00-AR0F AR10 AR11 AR12 AR13 AR14
Attribute Controller Registers
Function Color Data Registers Mode Control Register Overscan Color Register Memory Plane Enable Register Horizontal Pixel Panning Register Color Select Register Access read/write read/write read/write read/write read/write read/write Index 00-0F 10 11 12 13 14
To write to one of the attribute controller registers, the index of the desired register must be written to I/O address 3C0h and then the data is written to the very same I/O address. A flip-flop alternates with each write to I/O address 3C0h to change its function from writing the index to writing the actual data and back again. This flip-flop may be deliberately set so that I/O address 3C0h is set to write to the index (which provides a way to set it to a known state) by performing a read operation from Input Status Register 1 (ST01) at I/O address 3BAh or 3DAh (depending on whether the graphics system has been set to emulate an MDA or a CGA). To read from one of the attribute controller registers, the index of the desired register must be written to I/O address 3C0h and then the data is read from I/O address 3C1h. A read operation from I/O address 3C1h does not reset the flip-flop to writing to the index. Only a write to 3C0h or a read from 3BAh or 3DAh, as described above, will toggle the flip-flop back to writing to the index.
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Attribute Controller Registers
ARX
7
Attribute Controller Index Register
6 Reserved 5 Video Enable 4 3 2 1 0 Attribute Controller Register Index
read/write at I/O address 3C0h
Note: AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words "plane," "color plane," "display memory plane," and "memory map" have been all been used in IBM literature on the VGA standard to describe the four separate regions in the frame buffer where the pixel color or attribute information is split up and stored in standard VGA planar modes. This use of multiple terms for the same subject was deemed to be confusing, therefore AR12 is called the Memory Plane Enable Register. 7-6 5 Reserved Video Enable 0: Disables video, allowing the attribute controller color registers (AR00-AR0F) to be accessed by the CPU. 1: Enables video, causing the attribute controller color registers (AR00-AR0F) to be rendered inaccessible by the CPU. Note: In the VGA standard, this is called the "Palette Address Source" bit. Attribute Controller Register Index These five bits are used to select any one of the attribute controller registers, AR00 through AR14, to be accessed.
4-0
AR00-AR0F
7 A B Reserved Reserved 6
Palette Registers 0-F
5 4 3 2 1 0
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 00h to 0Fh shadowed for pipeline A and B
Palette Bits P5-P0 Palette Bits P5-P0
Note: Bits 3 and 2 of the Color Select Register (AR14) supply bits P7 and P6 for the values contained in all 16 of these registers. Bits 1 and 0 of the Color Select Register (AR14) can also replace bits P5 and P4 for the values contained in all 16 of these registers if bit 7 of the Mode Control Register (AR10) is set to 1. 7-6 5-0 Reserved Palette Bits P5-P0 In each of these 16 registers, these are the lower 6 of 8 bits that are used to map either text attributes or pixel color input values (for modes that use 16 colors) to the 256 possible colors available to be selected in the palette.
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Attribute Controller Registers
12-3
AR10
7 A
Mode Control Register
6 Pixel Width/ Clk Select Pixel Width/ Clk Select 5 Pixel Panning Compat Pixel Panning Compat 4 Reserved 3 En Blink/ Select Bkgnd Int En Blink/ Select Bkgnd Int 2 En Line Gr Char Code En Line Gr Char Code 1 Select Display Type Select Display Type 0 Graphics/ Alpha Mode Graphics/ Alpha Mode
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 10h shadowed for pipelines A and B
Palette Bits P5, P4 Select Palette Bits P5, P4 Select
B
Reserved
7
Palette Bits P5, P4 Select 0: P5 and P4 for each of the 16 selected colors (for modes that use 16 colors) are individually provided by bits 5 and 4 of their corresponding Palette Registers (AR00-0F). 1: P5 and P4 for all 16 of the selected colors (for modes that use 16 colors) are provided by bits 1 and 0 of Color Select Register (AR14). Pixel Width/Clock Select 0: Six bits of video data (translated from 4 bits via the palette) are output every dot clock. 1: Two sets of 4 bits of data are assembled to generate 8 bits of video data which is output every other dot clock, and the Palette Registers (AR00-0F) are bypassed. Note: This bit is set to 0 for all of the standard VGA modes, except mode 13h. Pixel Panning Compatibility 0: Scroll both the upper and lower screen regions horizontally as specified in the Horizontal Pixel Panning Register (AR13). 1: Scroll only the upper screen region horizontally as specified in the Horizontal Pixel Panning Register (AR13). Note: This bit has application only when split-screen mode is being used, where the display area is divided into distinct upper and lower regions which function somewhat like separate displays.
6
5
4 3
Reserved Enable Blinking/Select Background Intensity 0: Disables blinking in graphics modes and, in text modes, sets bit 7 of the character attribute bytes to control background intensity, instead of blinking. 1: Enables blinking in graphics modes and, in text modes, sets bit 7 of the character attribute bytes to control blinking, instead of background intensity. Note: The blinking rate is derived by dividing the VSYNC signal. The Blink Rate Control Register (FR19) defines the blinking rate.
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12-4 2
Attribute Controller Registers Enable Line Graphics Character Code 0: Every 9th pixel of a horizontal line (i.e., the last pixel of each horizontal line of each 9pixel wide character box) is assigned the same attributes as the background of the character of which the given pixel is a part. 1: Every 9th pixel of a horizontal line (i.e., the last pixel of each horizontal line of each 9pixel wide character box) is assigned the same attributes as the 8th pixel if the character of which the given pixel is a part. This setting is intended to accommodate the line-drawing characters of the PC's extended ASCII character set -- characters with an extended ASCII code in the range of B0h to DFh. Note: In IBM literature describing the VGA standard, the range of extended ASCII codes that are said to include the line-drawing characters is mistakenly specified as C0h to DFh, rather than the correct range of B0h to DFh.
1
Select Display Type 0: Attribute bytes in text modes are interpreted as they would be for a color display. 1: Attribute bytes in text modes are interpreted as they would be for a monochrome display. Graphics/Alphanumeric Mode 0: Selects alphanumeric (text) mode. 1: Selects graphics mode.
0
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Attribute Controller Registers
12-5
AR11
7 A B
Overscan Color Register
6 5 4 3 2 1 0
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 11h shadowed for pipelines A and B
Overscan Color Overscan Color
7-0
Overscan These 8 bits select the overscan (border) color. The border color is displayed during the blanking intervals. For monochrome displays, this value should be set to 00h.
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12-6
Attribute Controller Registers
AR12
7 A B
Memory Plane Enable Register
6 Reserved Reserved 5 4 3 Enable Plane 3 Enable Plane 3 2 Enable Plane 2 Enable Plane 2 1 Enable Plane 1 Enable Plane 1 0 Enable Plane 0 Enable Plane 0
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 12h shadowed for pipelines A and B
Video Status Mux Video Status Mux
Note: AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words "plane," "color plane," "display memory plane," and "memory map" have been all been used in IBM literature on the VGA standard to describe the 4 separate regions in the frame buffer that are amongst which pixel color or attributes information is split up and stored in standard VGA planar modes. This use of multiple terms for the same subject was deemed to be confusing, therefore AR12 is called the Memory Plane Enable Register. 7-6 5-4 Reserved Video Status Mux These 2 bits are used to select 2 of the 8 possible palette bits (P7-P0) to be made available to be read via bits 5 and 4 of the Input Status Register 1 (ST01). The table below shows the possible choices.
AR12 Bit 54 00 01 10 11
ST01 Bit 54 P2 P0 P5 P4 P3 P1 P7 P6
Note: These bits are largely unused by current software. They are provided for EGA compatibility. 3-0 Enable Plane 3-0 These 4 bits individually enable the use of each of the 4 memory planes in providing 1 of the 4 bits used in video output to select 1 of 16 possible colors from the palette to be displayed. 0: Disables the use of the corresponding memory plane in video output to select colors, forcing the bit that the corresponding memory plane would have provided to a value of 0. 1: Enables the use of the corresponding memory plane in video output to select colors.
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Attribute Controller Registers
12-7
AR13
7 A B
Horizontal Pixel Panning Register
6 Reserved Reserved 5 4 3 2 1 0
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 13h shadowed for pipelines A and B
Horizontal Pixel Shift Horizontal Pixel Shift
7-4 3-0
Reserved Horizontal Pixel Shift Bits 3-0 of this register hold a 4-bit value that selects number of pixels by which the image is shifted horizontally to the left. This function is available in both text and graphics modes. In text modes with a 9-pixel wide character box, the image can be shifted up to 8 pixels to the left. In text modes with an 8-pixel wide character box, and in graphics modes other than those with 256 colors, the image can be shifted up to 7 pixels to the left. In standard VGA mode 13h (where bit 6 of the Mode Control Register, AR10, is set to 1 to support 256 colors), bit 0 of this register must remain set to 0, and the image may be shifted up to only 3 pixels to the left. In this mode, the number of pixels by which the image is shifted can be further controlled using bits 6 and 5 of the Preset Row Scan Register (CR08).
Number of Pixels Shifted Value in Bits 3-0 0h 1h 2h 3h 4h 5h 6h 7h 8h 9 Pixel Text 1 2 3 4 5 6 7 8 0 8-Pixel Text & Graphics 0 1 2 3 4 5 6 7 Undefined 256-Color Graphics 0 Undefined 1 Undefined 2 Undefined 3 Undefined Undefined
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Attribute Controller Registers
AR14
7 A B
Color Select Register
6 Reserved Reserved 5 4 3 P7 P7 2 P6 P6 1 Alt P5 Alt P5 0 Alt P4 Alt P4
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 14h shadowed for pipelines A and B
7-4 3-2
Reserved Palette Bits P7 and P6 These are the 2 upper-most of the 8 bits that are used to map either text attributes or pixel color input values (for modes that use 16 colors) to the 256 possible colors contained in the palette. These 2 bits are common to all 16 sets of bits P5 through P0 that are individually supplied by Palette Registers 0-F (AR00-AR0F). Alternate Palette Bits P5 and P4 These 2 bits can be used as an alternate version of palette bits P5 and P4. Unlike the P5 and P4 bits that are individually supplied by Palette Registers 0-F (AR00-AR0F), these 2 alternate palette bits are common to all 16 of Palette Registers. Bit 7 of the Mode Control Register (AR10) is used to select between the use of either the P5 and P4 bits that are individually supplied by the 16 Palette Registers or these 2 alternate palette bits.
1-0
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Palette Registers
13-1
Chapter 13 Palette Registers
Introduction
The original VGA graphics system and earlier compatible ones had a distinct IC called either the RAMDAC or the palette DAC. The RAMDAC was made up of two main components: a 256x24bit color lookup table (CLUT) or palette in which a selection of 256 colors may be stored and a set of three digital-to-analog converters (DACs), one each for the red, green and blue components used to produce a color on a CRT display. Despite the integration of both the palette and the triplet of DACs into larger ICs in many present day graphics systems, the terms RAMDAC and palette DAC remain in common use. Table 13-1:
Name PALMASK PALSTATE PALRX PALWX PALDATA
Palette Registers
Function Palette Data Mask Register Palette State Register Palette Read Index Register Palette Write Index Register Palette Data Register Access read/write read-only write-only read/write read/write I/O Address 3C6h 3C7h 3C7h 3C8h 3C9h
However, this integration of both the palette and DACs into the graphics controller makes the use of such terms as RAMDAC and palette DAC erroneous, especially in the case of this graphics controller. This graphics controller has two outputs: the DACs which are normally used to drive a CRT display, and a flatpanel interface that is normally used to drive LCD or other types of flat panel displays. Either one or both of these outputs may be used at any given time and the pixel data sent to one or both of these outputs may or may not be routed through the palette. In short, the palette and DACs of this graphics controller can be used entirely independently of each other and for this reason, these registers have been renamed in a manner more in keeping with their actual purpose (e.g., the original VGA standard name of `DACSTATE' has been replaced with `PALSTATE'). Color Depths and the Palette Whether or not the palette is used depends entirely on the color depth to which the graphics system has been set via bits 3-0 of XR81. The palette is NOT used for modes with color depths greater than 8 bits per pixel. The data stored in the frame buffer is the actual color data, not an index. The appropriate bits describing the intensities of the red, green and blue components are retrieved from the frame buffer and routed to whichever output is being used. The palette is entirely bypassed, and so these are referred to as direct-color modes. The palette is used for modes with color depths of 8 bits per pixel or less. The color data stored in the frame buffer and received by the palette is actually an index that selects a location within the palette in which the components of a color is specified. The 3-bytes of the selected color are sent from the palette to whichever output (CRT or flat panel or both) is being used. Due to this use of an index into a palette, these modes are referred to as indexed modes. The use of indexed modes allows the main display image to take up less space in the frame buffer and allows the actual displayed colors to be specified independently. The latter feature has been known to be used in such applications as video games.
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13-2
Palette Registers
Accessing Color Data Locations Within the Palette A complex sub-indexing scheme using separate read and write access indices and a data port is used to access both the standard and alternate palette locations within the palette where color data is stored. The Palette Read Index Register is used to select the palette location to be read from via the Palette Data Register, while the Palette Write Index Register is used to select the palette location to be written to. This arrangement allows the same data port to be used for reading from and writing to two different palette locations. To read a palette location, the index of the desired palette location must first be written to the Palette Read Index Register. Then all three bytes of data in that palette location may be read, one at a time, via the Palette Data Register. The first byte read from the Palette Data Register retrieves the 8-bit value specifying the intensity of the red color component while the second and third byte reads are for the green and blue color components, respectively. After completing the third read operation, the Palette Read Index Register is automatically incremented so that the data of the next palette location becomes accessible for being read. This allows the contents of all 256 palette locations to be read by specifying only the index of the 0th location in the Palette Read Index Register, and then simply performing 768 successive reads from the Palette Data Register. Writing palette locations entails a very similar procedure. The index of the desired palette location must first be written to the Palette Write Index Register. Then all three bytes of data to specify a given color may be written, one at a time, to the selected palette location via the Palette Data Register. The first byte written to the Palette Data Register specifies the intensity of the red color component, while the second and third byte writes are for the green and blue color components, respectively. One important detail is that all three of these bytes must be written before the hardware will actually update these three values in the selected palette location. When all three bytes have been written, the Palette Write Index Register is automatically incremented so that the next palette location becomes accessible for being written. This allows the contents of all 256 palette locations to be written by specifying only the index of the 0th palette location in the Palette Write Index Register, and then simply performing 768 successive writes to the Palette Data Register. In addition to the standard set of 256 palette locations, there is also an alternate set of 8 palette locations used to specify the colors used to draw cursors 1 and 2, and these are also accessed using the very same sub-indexing scheme. Bit 0 of the Pixel Pipeline Configuration 0 Register (XR80) determines whether the standard 256 palette locations or the alternate 8 palette locations are to be accessed.
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Palette Registers
13-3
PALMASK
7 A B
Palette Data Mask Register
6 5 4 3 2 1 0
read/write at I/O address 3C6h shadowed for pipelines A and B
Pixel Data Mask Pixel Data Mask
7-0
Pixel Data Mask In indexed-color mode, the 8 bits of this register are logically ANDed with the 8 bits of pixel data received from the frame buffer for each pixel. The result of this ANDing process becomes the actual index used to select locations within the palette. This has the effect of limiting the choice of palette locations that may be specified by the incoming 8-bit data. In direct-color mode, the palette is not used, and the data in this register is entirely ignored.
PALSTATE
7 A B
Palette State Register
6 5 Reserved Reserved 4 3 2 1 DAC State DAC State 0
read-only at I/O address 3C7h shadowed for pipelines A and B
7-2 1-0
Reserved Palette State These 2 bits indicate which of the palette two index registers was most recently written to.
Bit 10 00 01 10 11 Palette Index Register Last Written To Palette Write Index Register (PALWX) at I/O address 3C8h reserved reserved Palette Read Index Register (PALRX) at I/O address 3C7h
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Palette Registers
PALRX
7 A B
Palette Read Index Register
6 5 4 3 2 1 0
write-only at I/O address 3C7h shadowed for pipelines A and B
Palette Read Index Palette Read Index
7-0
Palette Read Index This 8-bit value is an index that selects 1 of the 256 standard locations within the palette (or 1 of 8 alternate locations specifically for hardware cursor and popup colors, depending on the setting of bit 0 of XR80) to be read from via the Palette Data Register (PALDATA). The index value held in this register is automatically incremented when all three bytes of the color data position selected by the current index have been read.
PALWX
7 A B
Palette Write Index Register
6 5 4 3 2 1 0
read/write at I/O address 3C8 shadowed for pipelines A and B
Palette Write Index Palette Write Index
7-0
Palette Write Index This 8-bit value is an index that selects 1 of the 256 standard locations within the palette (or 1 of 8 alternate locations specifically for hardware cursor and popup colors, depending on the setting of bit 0 of XR80) to be written to via the Palette Data Register (PALDATA). The index value held in this register is automatically incremented when all three bytes of the color data position selected by the current index have been written.
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Palette Registers
13-5
PALDATA
7 A B
Palette Data Register
6 5 4 Palette Data Palette Data 3 2 1 0
read/write at I/O address 3C9h shadowed for pipelines A and B
7-0
Palette Data Register This byte-wide data port provides read or write access to the three bytes of data carried by palette location selected using the Palette Read Index Register (PALRX) or the Palette Write Index Register (PALWX). The three bytes in each palette location are written to or read from by making three successive read or write operations. The first byte read or written always specifies the intensity of the red component of the color specified in the selected palette location. The second byte is always for the green component and the third byte is always for the blue component. When writing data to a palette location, all three bytes must be written before the hardware will actually update the three bytes in that palette location. When reading or writing to a palette location, it is important to ensure that neither the Palette Read Index Register (PALRX) or the Palette Write Index Register (PALWX) are written to before all three bytes are read or written. The logic that automatically cycles through providing access to the bytes for the red, green and blue color components is reset to start again with the red component after writing to either PALRX or PALWX.
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Palette Registers
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Extension Registers
14-1
Chapter 14 Extension Registers
Introduction
Chapter 14 describes the Extension Registers for the 69030 Dual HiQVideo Accelerator. Table 14-1:
Name XR00 XR01 XR02 XR03 XR04 XR05 XR06 XR08 XR09 XR0A XR0B XR0E XR20 XR40 XR41-XR4F XR60 XR61 XR62 XR63 XR67 XR70 XR71 XR80 XR81 XR82 XR90-XR95 XRA0 XRA1 XRA2 XRA3 XRA4 XRA5 XRA6 XRA7 XRA8 XRA9
Extension Registers
Register Function Vendor ID Low Register Vendor ID High Register Device ID Low Register Device ID High Register Revision ID Register Linear Base Address Low Register Linear Base Address High Register Host Bus Configuration Register I/O Control Register Frame Buffer Mapping Register PCI Burst Write Support Register Frame Buffer Page Select Register BitBLT Configuration Register Memory Access Control Register Memory Configuration Registers Video Pin Control Register DPMS Sync Control Register GPIO Pin Control Register GPIO Pin Data Register Pin Tri-State Control Register Configuration Pins 0 Register Configuration Pins 1 Register Pixel Pipeline Configuration 0 Register Pixel Pipeline Configuration 1 Register Pixel Pipeline Configuration 2 Register Software Flag Registers Cursor 1 Control Register Cursor 1 Vertical Extension Register Cursor 1 Base Address Low Register Cursor 1 Base Address High Register Cursor 1 X-Position Low Register Cursor 1 X-Position High Register Cursor 1 Y-Position Low Register Cursor 1 Y-Position High Register Cursor 2 Control Register Cursor 2 Vertical Extension Register Access Via Port 3D7 read-only read-only read-only read-only read-only read-only read-only read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Index Value Port 3D6 (XRX) 00h 01h 02h 03h 04h 05h 06h 08h 09h 0Ah 0Bh 0Eh 20h 40h 41h-4Fh 60h 61h 62h 63h 67h 70h 71h 80h 81h 82h 90h-95h A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h
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14-2 Table 14-1:
XRAA XRAB XRAC XRAD XRAE XRAF XRC0 XRC1 XRC3 XRC4 XRC5 XRC7 XRC8 XRC9 XRCB XRCC XRCD XRCE XRCF XRD0 XRD1 XRD2 XRE0-XRE3 XRE4-XREF XRF8-XRFC
Extension Registers Extension Registers (Continued)
Cursor 2 Base Address Low Register Cursor 2 Base Address High Register Cursor 2 X-Position Low Register Cursor 2 X-Position High Register Cursor 2 Y-Position Low Register Cursor 2 Y-Position High Register Dot Clock 0 VCO M-Divisor Low Register Dot Clock 0 VCO N-Divisor Low Register Dot Clock 0 Divisor Select Register Dot Clock 1 VCO M-Divisor Low Register Dot Clock 1 VCO N-Divisor Low Register Dot Clock 1 Divisor Select Register Dot Clock 2 VCO M-Divisor Low Register Dot Clock 2 VCO N-Divisor Low Register Dot Clock 2 Divisor Select Register Memory Clock VCO M-Divisor Register Memory Clock VCO N-Divisor Register Memory Clock VCO Divisor Select Register Clock Configuration Register Powerdown Control Register Power Conservation Control Register 2KHz Down Counter Register Software Flag Registers 0 to 3 (shadowed) Software Flag Registers 4 to F (shared) Test Registers read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read/write read/write read/write AAh ABh ACh ADh AEh AFh C0h C1h C3h C4h C5h C7h C8h C9h CBh CCh CDh CEh CFh D0h D1h D2h E0h-E3h E4h-EFh F8h-FCh
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Extension Registers
14-3
XRX
7
Extension Register Index Register
6 5 4 3 2 1 0
read/write at I/O address 3D6h This register is cleared to 00h by reset.
Extension Register Index (0000:0000)
7-0
Extension Register Index These 8 bits are used to select any one of the extension registers to be accessed via the data port at I/O location 3D7h.
XR00
7 A & B
Vendor ID Low Register
6 5 4 3 2 1 0
read-only at I/O address 3D7h with index at I/O address 3D6h set to 00h shared by both pipelines A and B
Vendor ID Bits 7-0 (2Ch)
7-0
Vendor ID Bits 7-0 These 8 bits always carry the value 2Ch. This is the lower byte of CHIPS vendor ID for PCI devices. Both bytes of this ID are also readable from the Vendor ID register at offset 00h in the PCI configuration space.
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14-4
Extension Registers
XR01
7 A & B
Vendor ID High Register
6 5 4 3 2 1 0
read-only at I/O address 3D7h with index at I/O address 3D6h set to 01h shared by both pipelines A and B
Vendor ID Bits 15-8 (10h)
7-0
Vendor ID Bits 15-8 These 8 bits always carry the value 10h. This is the upper byte of CHIPS vendor ID for PCI devices. Both bytes of this ID are also readable from the Vendor ID register at offset 00h in the PCI configuration space.
XR02
7 A & B
Device ID Low Register
6 5 4 3 2 1 0
read-only at I/O address 3D7h with index at I/O address 3D6h set to 02h shared by both pipelines A and B
Device ID Bits 7-0 (30h)
7-0
Device ID Bits 7-0 These bits always carry the value 30h. This is the lower byte of this graphics controller's device ID as a PCI device. Both bytes of this ID are also readable from the Device ID register at offset 02h in the PCI configuration space
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Extension Registers
14-5
XR03
7 A & B
Device ID High Register
6 5 4 3 2 1 0
read-only at I/O address 3D7h with index at I/O address 3D6h set to 03h shared by both pipelines A and B
Device ID High (0Ch)
7-0
Device ID High These bits always carry the value 0Ch. This is the upper byte of this graphics controllers device ID as a PCI device. Both bytes of this ID are also readable from the Device ID register at offset 02h in the PCI configuration space
XR04
7 A & B
Revision ID Register
6 5 4 3 2 1 0
read-only at I/O address 3D7h with index at I/O address 3D6h set to 04h shared by both pipelines A and B
Chip Manufacturing Code (xxxx) Chip Revision Code (xxxx)
Note: This register is identical to the Revision register (REV) at offset 08h in the PCI configuration space. Note: The default value of this register is 61h. 7-4 3-0 Chip Manufacturing Code These four bits carry the fabrication code. Chip Revision Code These four bits carry the revision code. Revision codes start at 0 and are incremented for each new silicon revision.
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Extension Registers
XR05
7 A & B
Linear Base Address Low Register
6 5 4 3 Reserved (000:0000) 2 1 0
read-only at I/O address 3D7h with index at I/O address 3D6h set to 05h shared by both pipelines A and B
Mem Space Base Bit 23 (0)
7
Memory Space Base Address Bit 23 This bit is provided only for backward compatibility only. It is a hold-over from earlier CHIPS graphics controllers. The graphics controller requires a 16MB memory space on the host bus through which the linear frame buffer and memory-mapped registers are accessed. This 16MB memory space always begins on a 16MB address boundary, so bit 23 of the linear base address of this 16MB memory space always has the value of 0. Therefore this bit always returns the value of 0 when read. This base address is set through the MBASE register at offset 10h in the PCI configuration space.
6-0
Reserved These bits always return the value of 0 when read.
XR06
7 A & B
Linear Base Address High Register
6 5 4 3 2 1 0
read-only at I/O address 3D7h with index at I/O address 3D6h set to 06h shared by both pipelines A and B
Memory Space Base Address Bits 31-24 (xxxx:xxxx)
7-0
Memory Space Base Address Bits 31-24 The graphics controller requires a 16MB memory space on the host bus through which the linear frame buffer and memory-mapped registers are accessed. These 8 bits provide read-only access to bits 31-24, the 8 most significant bits of the linear base address at which the 16MB memory space begins. This base address is set through the MBASE register at offset 10h in the PCI configuration space.
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14-7
XR08
7 A & B
Host Bus Configuration Register
6 5 Reserved (0000:00) 4 3 2 1 PCI VGA Addr Dec (x) 0 Reserved (0)
read-only at I/O address 3D7h with index at I/O address 3D6h set to 08h shared by both pipelines A and B
7-2 1
Reserved These bits always return the value of 0 when read. PCI VGA Address Decode Enable This bit reflects the state of memory interface address pin CFG1 during reset. 0: Indicates that VGA I/O Address decoding is disabled on the PCI Bus, so access to the registers via I/O read and write operations is disabled. 1: Indicates that VGA I/O Address decoding is enabled on the PCI Bus, so access to the registers via I/O read and write operations is enabled. Note: The reset state of this pin is also readable via bit 1 of the Configuration Pins 0 Register (XR70).
0
Reserved This bit always returns the value of 0 when read.
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14-8
Extension Registers
XR09
7 A
I/O Control Register
6 5 4 Reserved (0000:000) Reserved 3 2 1 0 CRT Ctrl Ext Enable (0) CRT Ctrl Ext Enable (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 09h shadowed for pipelines A and B
B (0000:000)
7-1
Reserved These bits always return the value of 0 when read. CRT Controller Extensions Enable 0: Use only the CRT controller registers defined in the VGA standard to extend the number of bits used to specify the timing, resolution and addressing parameters to beyond eight bits. This is the default after reset. 1: Use only the additional Intel CRT controller registers to extend the number of bits used to specify the timing, resolution and addressing parameters to beyond eight bits.
0
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XR0A
7 A & B
Frame Buffer Mapping Register
6 Reserved (00) 5 4 3 Reserved (0) 2 Planar to Non X-late (0) 1 Linear Mapping (0) 0 Paged Mapping (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Ah shared by both pipelines A and B
Endian Byte Swapping Control (00)
7-6 5-4
Reserved These bits always return the value of 0 when read. Endian Byte Swapping Control These 2 bits enable and select the type of byte-swapping performed on all word and doubleword data written to and read from the graphics controller by the CPU as follows:
Bits 54 00 01 10 11
Type of Endian Byte Swapping No byte swapping. This is the default after reset. Performs byte swapping wherein byte 0 is swapped with byte 1 and byte 2 is swapped with byte 3. Performs byte swapping wherein byte 0 is swapped with byte 3 and byte 1 is swapped with byte 2. Reserved
3 2
Reserved This bit always returns the value of 0 when read. Planar to Non-Planar Address Translation Enable This bit provides a single-bit switch that can be used to alter the manner in which the frame buffer memory appears from the perspective of the host bus to be organized so that it looks as though the bits for each pixel are organized sequentially rather than in planes, even though it may well still be organized in planes. This is done through a hardware-based address translation scheme. The result is intended to be very similar to setting the frame buffer memory to chain-4 mode using the graphics controller registers. This switch is meant to be turned on occasionally as a convenience to programmers when the graphics controller is being used in standard VGA modes, in order to allow a given drawing operation or frame buffer save or restore operation to be carried out more easily. Altering this bit has no effect on the settings in the graphics controller registers (the GRxx series registers) that are normally used to specify the way in which the frame buffer memory is organized. It is recommended, however, that bits 3 and 2 of the Miscellaneous Register (GR06) be set so that the frame buffer memory is accessible using the A0000-AFFFF memory space during the time that this feature is used. 0: Disables address translation in support of packed mode. This is the default after reset. 1: Enables address translation in support of packed mode.
efmp69030 Databook
Revision 1.3 11/24/99
14-10 1
Extension Registers Frame Buffer Linear Mapping Enable 0: Disables the linear mapping of the frame buffer. 1: Enables the linear mapping of the frame buffer. Frame Buffer Page Mapping Enable 0: Disables the mapping of the frame buffer in 64KB pages into the A0000h-AFFFFh memory address space. 1: Enables the mapping of the frame buffer in 64KB pages into the A0000h-AFFFFh memory address space. Note: The selection of which 64KB page is to be mapped into memory addresses A0000hAFFFFh is made using bits 6-0 of the Frame Buffer Page Selector Register (XR0E).
0
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-11
XR0B
7
PCI Burst Write Support Register
6 Reserved 5 4 3 Font Exp Burst Write Depth (0) 2 PCI Burst Write Depth (0) 1 Reserved 0 Burst Write Enable (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Bh shared by both pipelines A and B
A & B
(0000)
(0)
7-4 3
Reserved These bits always return the value of 0 when read. Font Expansion PCI Burst Write Buffer Depth 0: The buffer used to receive PCI burst writes is always 4 or 8 doublewords deep as selected by bit 2 of this register, regardless of whether or not font expansion is being used. This is the default after a reset. 1: The buffer used to receive PCI burst writes is limited to being 1 doubleword deep when the font expansion feature is being used. PCI Burst Write Buffer Depth 0: The buffer used to receive PCI burst writes is set to be 8 doublewords deep. 1: The buffer used to receive PCI burst writes is set to be 4 doublewords deep. Note: The use of this bit to choose the depth of the PCI burst write buffer can be overridden by bit 3 of this register.
2
1 0
Reserved This bit always returns the value of 0 when read. PCI Burst Write Support Enable 0: Disables support for receiving PCI burst write cycles. 1: Enables support for receiving PCI burst write cycles.
efmp69030 Databook
Revision 1.3 11/24/99
14-12
Extension Registers
XR0E
7 A & B
Frame Buffer Page Select Register
6 5 4 3 Page Select (000:0000) 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Eh shared by both pipelines A and B
Reserved (0)
:7 6-0
Reserved This bit always returns the value of 0 when read. Page Select These seven bits select which 64KB page of the frame buffer is to be mapped into the A0000h-AFFFFh memory address space. Note: Bit 0 of the Address Mapping Register (XR0A) must be set to 1 to enable this mapping feature.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-13
XR20
7 A & B
BitBLT Configuration Register
6 Reserved (00) 5 4 3 2 1 BitBLT Reset (0) 0 BitBLT Status (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 20h shared by both pipelines A and B
BitBLT Engine Color Depth (00) Reserved (Writable) (00)
7-6 5-4
Reserved These bits always have the value of 0 when read. BitBLT Engine Color Depth When bit 23 of the BitBLT Control Register (BR04) is set to 0, these two bits configure the BitBLT engine for one of three possible color depths. If bit 23 of the BitBLT Control Register (BR04) is set to 1, then this function is performed by bits 25 and 24 of that same register. It is strongly recommended that the color depth of the BitBLT engine be set to match the color depth to which the graphics system has been set whenever possible.
Bits 54 00 01 10 11
BitBLT Engine Color Depth Selected 8 bits per pixel (1 byte per pixel) -- This is the default after reset. 16 bits per pixel (2 bytes per pixel) 24 bits per pixel (3 bytes per pixel) Reserved
The choice of color depth configures the BitBLT engine to work with one, two or three bytes per pixel. This directly affects the number of bytes of graphics data that the BitBLT engine will read and write for a given number of pixels. In the case of monochrome source or pattern data, this setting directly affects the color depth into which such monochrome data will be converted during the color expansion process. If the graphics system has been set to a color depth that is not supported by the BitBLT engine, then it is strongly recommended that the BitBLT engine not be used. See appendix B for more information. 3-2 1 Reserved (Writable) These bits should always be written to with the value of 0. BitBLT Reset 0: Writing a value of 0 to this bit permits normal operation of the BitBLT engine. This is the default value after reset. 1: Writing a value of 1 to this bit resets the BitBLT engine. BitBLT Engine Status 0: Indicates that the BitBLT engine is idle. This is the default after reset. 1: Indicates that the BitBLT engine is busy.
0
efmp69030 Databook
Revision 1.3 11/24/99
14-14
Extension Registers
XR40
7 A
Memory Access Control Register
6 5 4 3 2 1 Address Wrap (0) Address Wrap (0) 0 Memory Access (0) Memory Access (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 40h shadowed for pipeline A and B
Reserved (Writable) (0000:00) Reserved (Writable) B (0000:00)
7-2 1
Reserved (Writable) These bits should always be set to the value of 0. Address Wrap 0: Only bits 0 through 17 of the memory address decode are used, causing the memory address to wrap at 256K for all memory accesses either through the VGA porthole or linearly. 1: All memory address bits are used, allowing access to all of the graphics memory. Memory Access Width 0: Selects the use of 16-bit accesses to memory to accommodate the standard VGA modes and extended resolution modes with 4-bit color. This is the default after reset. 1: Selects the use of 64-bit accesses to memory to accommodate high resolution modes.
0
XR41-XR4F
7 A & B 6
Memory Configuration Registers
5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 41h to 4Fh shared by both pipelines A and B
Memory Configuration Bits (xxxx:xxxx)
7-0
Memory Configuration Bits The bits in each of these registers provide various ways to configure various aspects of the frame buffer. Each of these registers defaults to a particular setting, and some of these settings are nonzero. These default settings should NEVER be changed.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-15
XR60
7 A & B
Video Pin Control Register
6 PCLK Pin Source (0) 5 4 Reserved (00:00) 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 60h shared by both pipelines A and B
Reserved (0) Video Data Port Configuration (00)
7 6
Reserved This bit always returns the value of 0 when read. Video Data Port PCLK Pin Source 0: Selects the DCLK signal as the source. This is the default after reset. 1: Selects the DCLK signal, divided by 2, as the source. Reserved These bits always return the value of 0 when read. Video Data Port Configuration 00: Disables the video data port feature. 01: Enables the video data port and configures it to be used to support a standard VGA interface. 10: Reserved 11: Enables the video data port and configures it to be used to support a ZV-type feature connector.
5-2 1-0
efmp69030 Databook
Revision 1.3 11/24/99
14-16
Extension Registers
XR61
7 A & B
DPMS Sync Control Register
6 DPMS VSYNC (0) 5 DPMS HSYNC (0) 4 DPMS State Control (0) 3 DPMS VSYNC Sel (0) 2 DPMS VSYNC Data (0) 1 DPMS HSYNC Sel (0) 0 DPMS HSYNC Data (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 61h shared by both pipelines A and B
Reserved
(0)
7 6
Reserved This bit always has the value of 0 when read. DPMS VSYNC Output Select 2 0: The value carried by bit 2 of this register is output on the VSYNC pin. This is the default after reset. 1: The internal power sequencing clock is output on the VSYNC pin. DPMS HSYNC Output Select 2 0: The value carried by bit 0 of this register is output on the HSYNC pin. This is the default after reset. 1: The internal power sequencing clock is output on the HSYNC pin. DPMS HSYNC/VSYNC State Control 0: HSYNC and VSYNC pins are tri-stated during standby or panel-off modes. This is the default after reset. 1: HSYNC and VSYNC pins are driven during standby or panel-off modes with whatever data or signals that are selected by the other bits in this register. DPMS VSYNC Output Select 1 0: The VSYNC signal is output on the VSYNC pin. This is the default after reset. 1: Bit 6 of this register is used to select what is output on the VSYNC pin. DPMS VSYNC Output Data The value to which this bit is set is output on the VSYNC pin if bits 6 and 3 of this register are set to 0 and 1, respectively. DPMS HSYNC Output Select 1 0: The HSYNC signal is output on the HSYNC pin. This is the default after reset. 1: Bit 5 of this register is used to select what is output on the HSYNC pin. DPMS HSYNC Output Data The value to which this bit is set is output on the HSYNC pin if bits 5 and 1 of this register are set to 0 and 1, respectively.
5
4
3
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-17
XR62
7 A & B
GPIO Pin Control Register
6 Reserved (00) 5 4 Reserved 3 GPIO3 Direction (0) 2 GPIO2 Direction (0) 1 Reserved (00) 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 62h shared by both pipelines A and B
Reserved
Note: See the FP Pin Control 2 Register (FR0C) for direction control of GPIO0 and GPIO1. 7 6-5 4 3 Reserved Reserved These bits always return the value of 0 when read. Reserved GPIO3 Direction Control 0: GPIO3 acts as an input. This is the default after reset. 1: GPIO3 acts as an output. GPIO2 Direction Control 0: GPIO2 acts as an input. This is the default after reset. 1: GPIO2 acts as an output. Reserved These bits always return the value of 0 when read.
2
1-0
efmp69030 Databook
Revision 1.3 11/24/99
14-18
Extension Registers
XR63
7 A & B
GPIO Pin Data Register
6 Reserved (00) 5 4 Reserved 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 63h shared by both pipelines A and B
Reserved GPIO3 Data GPIO2 Data GPIO1 Data GPIO0 Data (x) (x) (x) (x)
7 6-5 4 3 2 1 0
Reserved Reserved These bits always return the value of 0 when read. Reserved GPIO3 Data This bit is used in either reading or setting the state of GPIO3. GPIO2 Data This bit is used in either reading or setting the state of GPIO2. GPIO1 Data This bit is used in either reading or setting the state of GPIO1. GPIO0 Data This bit is used in either reading or setting the state of GPIO0.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-19
XR67
7 A & B
Pin Tri-State Control Register
6 5 Reserved (0000:00) 4 3 2 1 Data Port Tri-State (0) 0 Reserved (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 67h shared by both pipelines A and B
7-2 1
Reserved These bits always return the value of 0 when read. Video Data Port Tri-State 0: Video data port pins are not tri-stated. This the default after reset. 1: Video data port pins are tri-stated. Reserved This bit should always be written to with a value of zero.
0
efmp69030 Databook
Revision 1.3 11/24/99
14-20
Extension Registers
XR70
7 A & B CFG7 (x)
Configuration Pins 0 Register
6 CFG6 (x) 5 CFG5 (x) 4 CFG4 (x) 3 CFG3 (x) 2 CFG2 (x) 1 CFG1 (x) 0 Reserved (1)
read-only at I/O address 3D7h with index at I/O address 3D6h set to 70h shared by both pipelines A and B
The bits of this register indicate the state of each of these pins at the time the graphics controller is reset. During a reset, the graphics controller does not drive these pins, thereby allowing them to either be pulled high by relatively weak internal resistors, or to be pulled low by external resistors (4.7K recommended). Instead, during reset, the graphics controller latches the state of these pins, and the latched values are used by the graphics controller to provide a limited degree of hardware-based configuration of some features. Some of these latched values directly affect the hardware, while others are simply reflected in this register so as to be read by configuration software, usually the BIOS. 7 Pin CFG7 0: Enables clock test mode. 1: Disables clock test mode. Note: Clock test mode allows the internal clock synthesizers to be tested, by placing the output of the MCLK synthesizer on the ROMOE# pin (the pin used to drive the chip select pin of the BIOS ROM) and the output of the VCLK synthesizer on the PCLK pin (the clock pin used for the video data port). 6 Pin CFG6 0: The ACTI and ENABKL outputs are forced to be tri-stated. 1: The ACTI and ENABKL outputs are permitted to function normally. Pin CFG5 Reserved. No interpretation has yet been assigned to the state of this bit, and the hardware does not interpret the state of the corresponding pin during reset. Pin CFG4 0: The MCLKIN and DCLKIN pins are used as inputs to receive MCLK an DCLK, respectively, from an external source. 1: MCLK and DCLK are provided by the internal clock generators. Note: The default selection of sources for MCLK and DCLK may be individually changed by changing the settings of bits 2 and 1 of the Memory Clock Divisor Select Register (XRCF). Both of those two bits also use the state of pin CFG_4 at reset to determine their default values.
5
4
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers 3
14-21
Pin CFG3 Reserved. No interpretation has yet been assigned to the state of this bit, and the hardware does not interpret the state of the corresponding pin during reset. Pin CFG2 Reserved. No interpretation has yet been assigned to the state of this bit, and the hardware does not interpret the state of the corresponding pin during reset. Pin CFG1 0: Indicates that VGA I/O Address decoding is disabled on the PCI Bus, so access to the registers via I/O read and write operations is disabled. 1: Indicates that VGA I/O Address decoding is enabled on the PCI Bus, so access to the registers via I/O read and write operations is enabled. Note: The reset state of this pin is also readable via bit 1 of the Host Bus Configuration Register (XR08).
2
1
0
Reserved This bit always returns the value of 1 when read.
efmp69030 Databook
Revision 1.3 11/24/99
14-22
Extension Registers
XR71
7 A & B CFG15 (x)
Configuration Pins 1 Register
6 CFG14 (x) 5 CFG13 (x) 4 CFG12 (x) 3 CFG11 (x) 2 CFG10 (x) 1 CFG9 (x) 0 CFG8 (x)
read-only at I/O address 3D7h with 3D6h set to Index 71h shared by both pipelines A and B
The bits of this register indicate the state of each of these pins at the time the graphics controller is reset. During a reset, the graphics controller does not drive these pins, thereby allowing them to either be pulled high by relatively weak internal resistors, or to be pulled low by external resistors (4.7K recommended). Instead, during reset, the graphics controller latches the state of these pins, and the latched values are used by the graphics controller to provide a limited degree of hardware-based configuration of some features. Some of these latched values directly affect the hardware, while others are simply reflected in this register so as to be read by configuration software, usually the BIOS. 7 Pin CFG15 Reserved. An individual interpretation has not been assigned to this bit, and the hardware does not interpret the state of the corresponding pin during reset. Pin CFG14 Reserved for BIOS for use as bit 3 of a 4-bit code specifying the panel type. Pin CFG13 Reserved for BIOS for use as bit 2 of a 4-bit code specifying the panel type. Pin CFG12 Reserved for BIOS for use as bit 1 of a 4-bit code specifying the panel type. Pin CFG11 Reserved for BIOS for use as bit 0 of a 4-bit code specifying the panel type. Pin CFG10 Reserved. An individual interpretation has not been assigned to this bit, and the hardware does not interpret the state of the corresponding pin during reset. Pin CFG9 0: Indicates that the upper memory space has been configured to provide single-pipe dualendian support. Pipeline A's memory space is repeated to provide both little-endian and a big-endian address ranges. 1: Indicates that the upper memory space has been configured to provide little-endian dualpipe support. Both pipeline A's and pipeline B's memory spaces are provided, and only in little endian. Pin CFG8 Reserved. An individual interpretation has not been assigned to this bit, and the hardware does not interpret the state of the corresponding pin during reset.
6 5 4 3 2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-23
XR80
7 A
Pixel Pipeline Configuration 0 Register
6 Reserved 5 Pixel Averaging (0) Pixel Averaging (0) 4 Alt Hardware Cursor En (0) Alt Hardware Cursor En (0) 3 Extended Status Read (0) Extended Status Read (0) 2 Flat Panel Overscan (0) Flat Panel Overscan (0) 1 CRT Overscan (0) CRT Overscan (0) 0 Palette Addr Select (0) Palette Addr Select (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 80h shadowed for pipelines A and B
6-Bit/8-Bit DAC Select (0) B 6-Bit/8-Bit DAC Selec (0)
(0) Reserved
(0)
7
6-Bit/8-Bit DAC Select 0: All three D-to-A converters are set for 6-bit operation. This is the default after reset. 1: All three D-to-A converters are set for 8-bit operation. Reserved This bit always returns the value of 0 when read. Pixel Averaging Enable Pixel averaging causes the red, green and blue color component values of a replicated pixel created by the horizontal stretching process to be averaged with those of the next pixel. 0: Disables pixel averaging. This is the default after reset. 1: Enables pixel averaging. Note: The pixel averaging feature applies only to flat panel displays, not CRT's, and it applies only when horizontal stretching is active (see the description of the Horizontal Stretching Register, FR41, for more details).
6 5
4
Alternate Hardware Cursor Enable 0: Disables hardware cursor. 1: Enables hardware cursor.
efmp69030 Databook
Revision 1.3 11/24/99
14-24 3
Extension Registers Extended Status Read Enable When enabled, the extended status read feature changes the functionality of three of the palette registers in order to allow the status of the internal state machines and values of the red and green data in the input holding register to be read. The affected palette registers and their alternate functions are as follows: 0: Disable extended status read feature. This is the default after reset. 1: Enable extended status read feature.
Affected Register Pixel Data Mask Register (PALMASK) Palette Write Mode Index Register (PALWX) Palette State Register (PALSTATE) Alternate Function Returns the value of the red pixel data currently in the data holding register. Returns the value of the green pixel data currently in the data holding register. Returns the status of the internal state machines in bits 7-2.
Note: This feature must be disabled to permit normal accesses to the registers and color data locations within the palette. 2 Flat Panel Overscan Color Enable 0: Disable the use of the flat panel overscan color (Overscan, bit 1). This is the default after reset. 1: Enable the use of the flat panel overscan color (Overscan, bit 1). CRT Overscan Enable 0: Disable the use of the CRT overscan color (Overscan, bit 0). This is the default after reset. 1: Enable the use of the CRT overscan color (Overscan, bit 0). Palette Addressing Select 0: Select the standard 256-position palette for the main display image to be accessed via the palette's sub-indexing scheme. This is the default after reset. 1: Select the separate 8-position palette for cursor 1 and cursor 2 to be accessed via the palette's sub-indexing scheme.
1
0
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-25
XR81
7 A
Pixel Pipeline Configuration 1 Register
6 Reserved (000) Reserved 5 4 VGA Std Delay (0) VGA Std Delay (0) 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 81h shadowed for pipelines A and B
Graphics System Color Depth (0000) Graphics System Color Depth (0000)
B (000)
7-5 4
Reserved These bits always return the value of 0 when read. VGA Standard Signal Delay Enable 0: The CRT Display Enable and CRT Blanking are delayed for compatibility with the VGA standard. The behavior of CR00 remains compatible with the VGA standard, inasmuch as the value placed there must be subtracted by 5. This is the default after reset. 1: The CRT Display Enable and CRT Blanking are not delayed. The behavior of CR00 is altered in a way that is different from the VGA standard, inasmuch as the value placed there is not to be subtracted by 5. Note: This enables/disables the delay of signals relative to the CRT horizontal and vertical sync signals. When the flat panel display engine is enabled (i.e., when bit 1 of FR01 is set to 1), then this bit is ignored and no such delay takes place.
3-0
Graphics System Color Depth
Bits 3210 0000 0001 0010 0011 0100 0101 0110 0111 1x xx Color Depth Selected for Graphics System Configures the CRT pipeline for standard VGA text and graphics modes, and for 1bpp, 2bpp and 4bpp extended graphics modes. This is the default after reset. Reserved Configures the CRT pipeline for 8bpp extended graphics modes. Reserved Configures the CRT pipeline for 16bpp extended graphics modes wherein the graphics data follows a fixed Targa-compatible 5-5-5 RGB format. Configures the CRT pipeline for 16bpp extended graphics modes wherein the graphics data follows a fixed XGA-compatible 5-6-5 RGB format. Configures the CRT pipeline for packed 24bpp extended graphics modes wherein only 3 bytes are allocated for each pixel. Configures the CRT pipeline for non-packed 24bpp (32bpp) extended graphics modes wherein 4 bytes are allocated for each pixel, so that the graphics data for each pixel is doubleword-aligned. The 4th byte allocated for each pixel is unused. Reserved
efmp69030 Databook
Revision 1.3 11/24/99
14-26
Extension Registers
XR82
7 A
Pixel Pipeline Configuration 2 Register
6 Reserved (0000) Reserved 5 4 3 Graphics Gamma (0) Graphics Gamma (0) 2 Video Gamma (0) Video Gamma (0) 1 Comp. Sync on Green (0) Comp. Sync on Green (0) 0 Blank Pedestal (0) Blank Pedestal (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to 82h shadowed for pipelines A and B
B (0000)
7-4 3
Reserved These bits always return the value of 0 when read. Graphics Data Gamma Correction Enable 0: Graphics data bypasses the palette when the graphics system is set to a color depth of 16, 24 or 32 bits per pixel. This is the default after reset. 1: Graphics data goes through the palette when the graphics system is set to a color depth of 16, 24 or 32 bits per pixel, allowing the palette to be used to perform gamma correction. Video Data Gamma Correction Enable 0: Video data bypasses the palette. This is the default after reset. 1: Video data goes through the palette, allowing the palette to be used to perform gamma correction. Composite Sync on Green Enable 0: Disables the provision of composite sync on the green analog output. This is the default after reset. 1: Enables the provision of composite sync on the green analog output. Blank Pedestal Enable 0: Disables the provision of a pedestal output level during blanking periods. This is the default after reset. 1: Enables the provision of a pedestal output level during blanking periods.
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-27
XR88
7 A & B
Alternate Font Location Control
6 Reserved (0) 5 Font Select (00) 4 3 2 1 Font Copy Stat & Trig (0) 0 Reserved (0)
read-only at I/O address 3D7h with 3D6h set to Index 88h shared by both pipelines A and B
Alt Font Location En (0) Pipeline Vertical Blanking Trigger Select (00)
7
Alternate Font Location Enable 0: Disables having the alternate font location in the frame buffer. 1: Enables having the alternate font location in the frame buffer. Reserved This bit always returns the value of 0 when read. Font Select These two bits select which fonts from VGA-compatible locations in plane 2 will be copied to the alternate font location.
Bits 54 00 01 10 11 Font Selected No fonts are selected, and all use of the alternate font location is disabled just as if bit 7 of this register were set to 0. Font A, the one pointed to by bits 5, 3 and 2 of SR03 is selected. Font B, the one pointed to by bits 4, 1 and 0 of SR03 is selected. Both fonts A and B (i.e., both the font pointed to by bits 5, 3 and 2 of SR03, and the font pointed to by bits 4, 1 and 0 of SR03) are selected.
6 5-4
3-2
Pipeline Vertical Blanking Trigger Select These two bits select which pipeline's vertical blanking events will be used to increment the counter that triggers the copying of fonts from VGA-compatible locations to the alternate font location.
Bits 54 00 01 10 11 Font Selected No fonts are selected, and all use of the alternate font location is disabled just as if bit 7 of this register were set to 0. Font A, the one pointed to by bits 5, 3 and 2 of SR03 is selected. Font B, the one pointed to by bits 4, 1 and 0 of SR03 is selected. Both fonts A and B (i.e., both the font pointed to by bits 5, 3 and 2 of SR03, and the font pointed to by bits 4, 1 and 0 of SR03) are selected.
1
Font Copy Status and Trigger When read, this bit indicates whether or not a copy operation is in progress. 0: No copy operation is currently in progress. 1: A copy operation is currently in progress. When written, this bit can be used to immediately trigger a copy operation regardless of the current state of the counter. 0: Does not immediately trigger a copy operation. Writing a 0 to this bit does nothing. 1: Immediately triggers a copy operation.
0
Reserved This bit always returns the value of 0 when read. Revision 1.3 11/24/99
efmp69030 Databook
14-28
Extension Registers
XR8A
7 A & B
Alternate Font Location Start Offset Low
6 5 4 3 2 1 Reserved (000) 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 8Ah shared by both pipelines A and B
Alternate Font Location Starting Offset Bits 15-11 (0000:0)
7-3
Alternate Font Location Start Offset Bits 15-11 These are the less significant bits of the offset from the beginning of the frame buffer at which the alternate font location begins. The most significant bits are carried by the 8 bits of XR8B. Reserved These bits always return the value of 0 when read.
2-0
XR8B
7 A & B
Alternate Font Location Start Offset High
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 8Bh shared by both pipelines A and B
Alternate Font Location Starting Offset Bits 23-16 (0000:0000)
7-0
Alternate Font Location Start Offset Bits 23--16 These are the most significant bits of the offset from the beginning of the frame buffer at which the alternate font location begins. The less significant bits are carried by bits 7 to 3 of XR8A.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-29
XR8C
7 A & B
Alternate Font Location Counter Trigger Count
6 Reserved (00) 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 8Ch shared by both pipelines A and B
Alternate Font Location Counter Trigger Count (00:0000)
7-6 5-0
Reserved These bits always return the value of 0 when read. Alternate Font Location Counter Trigger Count A counter is used to keep a count of the number of vertical blanking events that occur on the pipelines selected via bits 3 and 2 of XR88. When the counter reaches the value carried by these 6 bits of this register, the copying of fonts in VGA-compatible locations to the alternate blanking location is triggered. Note: If these 6 bits are all set to 0, the copying of fonts is disabled.
XR8E
7 A & B
Alternate Font Location Copy Read Burst Limit
6 Reserved (00) 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to 8Eh shared by both pipelines A and B
Alternate Font Location Copy Read Burst Limit (00:0000)
7-6 5-0
Reserved These bits always return the value of 0 when read. Alternate Font Location Copy Read Burst Limit These 6 bits are used to specify the number of 256-bit/64-bit blocks of font data that are to be copied each time the copying of fonts from VGA-compatible locations to the alternate font location is triggered. Note: Each subsequent copy operation begins immediately after the location (both at the source and destination) at which the last copy operation ended.
efmp69030 Databook
Revision 1.3 11/24/99
14-30
Extension Registers
XR90-XR95
7 A & B
Software Flag Registers
6 5 4 3 2 1 0
read/write at I/O Address 3D7h with 3D6h set to indexes 90h to 95h shared by both pipelines A and B
Shared Software Flag Bits (xxxx:xxxx)
7-0
Software Flag Bits
The bits in each of these eight registers are used largely as a "scratch pad" by Intel BIOS. To a limited extent, these registers are also used as a medium of communication between Intel BIOS and Intel device drivers for various operating system environments and should not be accessed for any other purpose.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-31
XRA0
7 A Cursor 1 Blink En (0) Cursor 1 Blink En (0)
Cursor 1 Control Register
6 Cursor 1 V Stretch (0) Cursor 1 V Stretch (0) 5 Cursor 1 H Stretch (0) Cursor 1 H Stretch (0) 4 Coordinate Origin Sel (0) Coordinate Origin Sel (0) 3 Vertical Extension (0) Vertical Extension (0) 2 1 Cursor 1 Mode Select (000) Cursor 1 Mode Select (000) 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A0h shadowed for pipelines A and B
B
7
Cursor 1 Blink Enable 0: Disables blinking. This is the default after reset. 1: Enables blinking. Blinking rate set in register FR19. Cursor 1 Vertical Stretching Enable 0: Disables vertical stretching for cursor 1. This is the default after reset. 1: Enables vertical stretching for cursor 1. Note: Just as is the case with the vertical stretching for the main display image, vertical stretching for cursor 1 applies only to flat panel displays.
6
5
Cursor 1 Horizontal Stretching Enable 0: Disables horizontal stretching for cursor 1. This is the default after reset. 1: Enables horizontal stretching for cursor 1. Note: Just as is the case with the horizontal stretching for the main display image, horizontal stretching for cursor 1 applies only to flat panel displays.
4
Cursor 1 Coordinate System Origin Select 0: Selects the outermost upper left-hand corner of the screen border as the origin for the coordinate system used to position cursor 1. This is the default after reset. 1: Selects the upper left-hand corner of the active display area as the origin for the coordinate system used to position cursor 1. Cursor 1 Vertical Extension Enable 0: Disables the vertical extension feature for cursor 1. This is the default after reset. 1: Enables the vertical extension feature for cursor 1, thereby permitting the height of cursor 1 may be specified independently of its mode selection through the use of the Cursor 1 Vertical Extension Register (XRA1).
3
efmp69030 Databook
Revision 1.3 11/24/99
14-32 2-0
Extension Registers Cursor 1 Mode Select These three bits select the mode for cursor 1. See appendix F for more details concerning the cursor modes.
Bits 210 000 001 010 011 100 101 110 111 Cursor Mode Cursor 1 is disabled. This is the default after reset. 32x32 2bpp AND/XOR 2-plane mode 128x128 1bpp 2-color mode 128x128 1bpp 1-color and transparency mode 64x64 2bpp 3-color and transparency mode 64x64 2bpp AND/XOR 2-plane mode 64x64 2bpp 4-color mode Reserved
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-33
XRA1
7 A B
Cursor 1 Vertical Extension Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A1h shadowed for pipelines A and B
Cursor 1 Vertical Extension (00h) Cursor 1 Vertical Extension (00h)
7-0
Cursor 1 Vertical Extension When the vertical extension feature for cursor 1 is enabled by setting bit 3 of the Cursor 1 Control Register (XRA0) to 1, these 8 bits of this register are used to specify the height of cursor 1 in scan lines. The number of scan lines must be a multiple of four. This register should be programmed with a value derived from the following equation: value = ((number of scanlines) / (4) - 1
XRA2
7 A B
Cursor 1 Base Address Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A2h shadowed for pipelines A and B
Cursor 1 Base Address Bits 15-12 (0000) Cursor 1 Base Address Bits 15-12 (0000) Cursor 1 Pattern Select (0000) Cursor 1 Pattern Select (0000)
7-4
Cursor 1 Base Address Bits 15-12 These four bits provide part of a 22-bit value that specifies the offset from the beginning of the frame buffer memory space where the 4KB cursor data space for cursor 1 is to be located. The six most-significant bits of this 22-bit value are supplied by the Cursor 1 Base Address High Register (XRA3). Cursor 1 Pattern Select These four bits allow 1 of up to as many as 16 possible patterns contained in the cursor data space for cursor 1 to be selected to be displayed. The actual number of patterns depends on the size of each pattern, since the cursor data space is limited to a total of 4KB in size. The size of each pattern depends, at least in part, on the choice of cursor mode. See appendix D for more details concerning the cursor modes.
3-0
efmp69030 Databook
Revision 1.3 11/24/99
14-34
Extension Registers
XRA3
7 A B
Cursor 1 Base Address High Register
6 Reserved (00) Reserved (00) 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A3h shadowed for pipelines A and B
Cursor 1 Base Address Bits 21-16 (00:0000) Cursor 1 Base Address Bits 21-16 (00:0000)
7-6 5-0
Reserved These bits always return the value of 0 when read. Cursor 1 Base Address Bits 21-16 These six bits provide the six most significant bits of a 22-bit value that specifies the offset from the beginning of the frame buffer memory space where the 4KB cursor data space for cursor 1 is to be located. The four next most-significant bits of this 22-bit value are supplied by the Cursor 1 Base Address Low Register (XRA2).
XRA4
7 A B
Cursor 1 X-Position Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A4h shadowed for pipelines A and B
Cursor 1 X-Position Magnitude Bits 7-0 (00h) Cursor 1 X-Position Magnitude Bits 7-0 (00h)
7-0
Cursor 1 X-Position Magnitude Bits 7-0 This register provides the eight least significant magnitude bits of a signed 12-bit value that specifies the horizontal position of cursor 1. The three most significant magnitude bits and the sign bit of this value are provided by bits 2-0 and bit 7, respectively, of the Cursor 1 XPosition High Register (XRA5).
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-35
XRA5
7 A
Cursor 1 X-Position High Register
6 5 Reserved (000:0) Reserved (000:0) 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A5h shadowed for pipelines A and B
X-Pos Sign Bit (0) X-Pos Sign Bit (0) Cursor 1 X-Position Magnitude Bits 10-8 (000) Cursor 1 X-Position Magnitude Bits 10-8 (000)
B
7
Cursor 1 X-Position Sign Bit This bit provides the sign bit of a signed 12-bit value that specifies the horizontal position of cursor 1. The magnitude bits are provided by the Cursor 1 X-Position Low Register (XRA4) and bits 2-0 of this register. Reserved These bits always return the value of 0 when read. Cursor 1 X-Position Magnitude Bits 10-8 These three bits provide the three most significant magnitude bits of a signed 12-bit value that specifies the horizontal position of cursor 1. The eight least significant magnitude bits of this value are provided by bits 7-0 of the Cursor 1 X-Position Low Register (XRA4). The sign bit is provided by bit 7 of this register.
6-3 2-0
XRA6
7 A B
Cursor 1 Y-Position Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A6h shadowed for pipelines A and B
Cursor 1 Y-Position Magnitude Bits 7-0 (00h) Cursor 1 Y-Position Magnitude Bits 7-0 (00h)
7-0
Cursor 1 Y-Position Magnitude Bits 7-0 This register provides the eight least significant magnitude bits of a signed 12-bit value that specifies the vertical position of cursor 1. The three most significant magnitude bits and the sign bit of this value are provided by bits 2-0 and bit 7, respectively, of the Cursor 1 YPosition High Register (XRA7).
efmp69030 Databook
Revision 1.3 11/24/99
14-36
Extension Registers
XRA7
7 A
Cursor 1 Y-Position High Register
6 5 Reserved (000:0) Reserved (000:0) 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A7h shadowed for pipelines A and B
Y-Pos Sign Bit (0) Y-Pos Sign Bit (0) Cursor 1 Y-Position Magnitude Bits 10-8 (000) Cursor 1 Y-Position Magnitude Bits 10-8 (000)
B
7
Cursor 1 Y-Position Sign Bit This bit provides the sign bit of a signed 12-bit value that specifies the horizontal position of cursor 1. The magnitude bits are provided by the Cursor 1 Y-Position Low Register (XRA6) and bits 2-0 of this register. Reserved These bits always return the value 0 when read. Cursor 1 Y-Position Magnitude Bits 10-8 These three bits provide the three most significant magnitude bits of a signed 12-bit value that specifies the vertical position of cursor 1. The eight least significant magnitude bits of this value are provided by bits 7-0 of the Cursor 1 Y-Position Low Register (XRA6). The sign bit is provided by bit 7 of this register.
6-3 2-0
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-37
XRA8
7 A & B Cursor 2 Blink En (0)
Cursor 2 Control Register
6 Cursor 2 V Stretch (0) 5 Cursor 2 H Stretch (0) 4 Coordinate Origin Sel (0) 3 Vertical Extension (0) 2 1 Cursor 2 Mode Select (000) 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A8h shared by both pipelines A and B
7
Cursor 2 Blink Enable 0: Disables blinking. This is the default after reset. 1: Enables blinking. Blinking rate set in register FR19. Cursor 2 Vertical Stretching Enable 0: Disables vertical stretching for cursor 2. This is the default after reset. 1: Enables vertical stretching for cursor 2. Note: Just as is the case with the vertical stretching for the main display image, vertical stretching for cursor 2 applies only to flat panel displays.
6
5
Cursor 2 Horizontal Stretching Enable 0: Disables horizontal stretching for cursor 2. This is the default after reset. 1: Enables horizontal stretching for cursor 2. Note: Just as is the case with the horizontal stretching for the main display image, horizontal stretching for cursor 2 applies only to flat panel displays.
4
Cursor 2 Coordinate System Origin Select 0: Selects the outermost upper left-hand corner of the screen border as the origin for the coordinate system used to position cursor 2. This is the default after reset. 1: Selects the upper left-hand corner of the active display area as the origin for the coordinate system used to position cursor 2. Cursor 2 Vertical Extension Enable 0: Disables the vertical extension feature for cursor 2. This is the default after reset. 1: Enables the vertical extension feature for cursor 2, thereby permitting the height of cursor 2 may be specified independently of its mode selection through the use of the Cursor 2 Vertical Extension Register (XRA9). Cursor 2 Mode Select These three bits select the mode for cursor 2. See appendix F for more details concerning the cursor modes.
Bits 210 000 001 010 011 100 101 110 111 Cursor Mode Cursor 2 is disabled. This is the default after reset. 32x32 2bpp AND/XOR 2-plane mode 128x128 1bpp 2-color mode 128x128 1bpp 1-color and transparency mode 64x64 2bpp 3-color and transparency mode 64x64 2bpp AND/XOR 2-plane mode 64x64 2bpp 4-color mode Reserved
3
2-0
efmp69030 Databook
Revision 1.3 11/24/99
14-38
Extension Registers
XRA9
7 A & B
Cursor 2 Vertical Extension Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to A9h shared by both pipelines A and B
Cursor 2 Vertical Extension (00h)
7-0
Cursor 2 Vertical Extension When the vertical extension feature for cursor 2 is enabled by setting bit 3 of the Cursor 2 Control Register (XRA8) to 1, these 8 bits of this register are used to specify the height of cursor 2 in scan lines. The number of scan lines must be a multiple of four. This register should be programmed with a value derived from the following equation: value = ((number of scanlines) / ( 4) - 1
XRAA
7 A & B
Cursor 2 Base Address Low Register
6 5 4 3 2 1 0
read/write at I/O Address 3D7h with index at I/O address 3D6h set to AAh shared by both pipelines A and B
Cursor 2 Base Address Bits 15-12 (0000) Cursor 2 Pattern Select (0000)
7-4
Cursor 2 Base Address Bits 15-12 These four bits provide part of a 22-bit value that specifies the offset from the beginning of the frame buffer memory space where the 4KB cursor data space for cursor 2 is to be located. The six most-significant bits of this 22-bit value are supplied by the Cursor 2 Base Address High Register (XRAB). Cursor 2 Pattern Select These four bits allow 1 of up to as many as 16 possible patterns contained in the cursor data space for cursor 2 to be selected to be displayed. The actual number of patterns depends on the size of each pattern, since the cursor data space is limited to a total of 4KB in size. The size of each pattern depends, at least in part, on the choice of cursor mode. See the section on the hardware cursor and popup for more details concerning the cursor modes.
3-0
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-39
XRAB
7 A & B
Cursor 2 Base Address High Register
6 Reserved (00) 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to ABh shared by both pipelines A and B
Cursor 2 Base Address Bits 21-16 (00:0000)
7-6 5-0
Reserved These bits always return the value of 0 when read. Cursor 2 Base Address Bits 21-16 These six bits provide the six most significant bits of a 22-bit value that specifies the offset from the beginning of the frame buffer memory space where the 4KB cursor data space for cursor 2 is to be located. The four next most-significant bits of this 22-bit value are supplied by the Cursor 2 Base Address Low Register (XRAA).
XRAC
7 A & B
Cursor 2 X-Position Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to ACh shared by both pipelines A and B
Cursor 2 X-Position Magnitude Bits 7-0 (00h)
7-0
Cursor 2 X-Position Magnitude Bits 7-0 This register provides the eight least significant magnitude bits of a signed 12-bit value that specifies the horizontal position of cursor 2. The three most significant magnitude bits and the sign bit of this value are provided by bits 2-0 and bit 7, respectively, of the Cursor 2 XPosition High Register (XRAD).
efmp69030 Databook
Revision 1.3 11/24/99
14-40
Extension Registers
XRAD
7 A & B X-Position Sign Bit (0)
Cursor 2 X-Position High Register
6 5 Reserved (000:0) 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to ADh shared by both pipelines A and B
Cursor 2 X-Position Magnitude Bits 10-8 (000)
7
Cursor 2 X-Position Sign Bit This bit provides the sign bit of a signed 12-bit value that specifies the horizontal position of cursor 2. The magnitude bits are provided by the Cursor 2 X-Position Low Register (XRAC) and bits 2-0 of this register. Reserved These bits always return the value of 0 when read. Cursor 2 X-Position Magnitude Bits 10-8 These three bits provide the three most significant magnitude bits of a signed 12-bit value that specifies the horizontal position of cursor 2. The eight least significant magnitude bits of this value are provided by bits 7-0 of the Cursor 2 X-Position Low Register (XRAC). The sign bit is provided by bit 7 of this register.
6-3 ` 2-0
XRAE
7 A & B
Cursor 2 Y-Position Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to AEh shared by both pipelines A and B
Cursor 2 Y-Position Magnitude Bits 7-0 (00h)
7-0
Cursor 2 Y-Position Magnitude Bits 7-0 This register provides the eight least significant magnitude bits of a signed 12-bit value that specifies the vertical position of cursor 2. The three most significant magnitude bits and the sign bit of this value are provided by bits 2-0 and bit 7, respectively, of the Cursor 2 YPosition High Register (XRAF).
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-41
XRAF
7 A & B
Cursor 2 Y-Position High Register
6 5 Reserved (000:0) 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to AFh shared by both pipelines A and B
Y-Position Sign Bit (0) Cursor 2 Y-Position Magnitude Bits 10-8 (000)
7
Cursor 2 Y-Position Sign Bit This bit provides the sign bit of a signed 12-bit value that specifies the vertical position of cursor 2. The magnitude bits are provided by the Cursor 2 Y-Position Low Register (XRAE) and bits 2-0 of this register. Reserved These bits always return the value of 0 when read. Cursor 2 Y-Position Magnitude Bits 10-8 These three bits provide the three most significant magnitude bits of a signed 12-bit value that specifies the vertical position of cursor 2. The eight least significant magnitude bits of this value are provided by bits 7-0 of the Cursor 2 Y-Position Low Register (XRAE). The sign bit is provided by bit 7 of this register.
6-3 2-0
XRC0
7 A & B
Dot Clock 0 VCO M-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to C0h shared by both pipelines A and B
Dot Clock 0 VCO M-Divisor
Note: All four of the registers used in specifying the loop parameters for dot clock 0 (XRC0 - XRC3) must be written, and in order from XRC0 to XRC3, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Dot Clock 0 VCO M-Divisor This register provides the M-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 0. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 0. See appendix B for a detailed description of the process used to derive the loop parameter values.
efmp69030 Databook
Revision 1.3 11/24/99
14-42
Extension Registers
XRC1
7 A & B
Dot Clock 0 VCO N-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to C1h shared by both pipelines A and B
Dot Clock 0 VCO N-Divisor
Note: All four of the registers used in specifying the loop parameters for dot clock 0 (XRC0 - XRC3) must be written, and in order from XRC0 to XRC3, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Dot Clock 0 VCO N-Divisor Bits 7-0 This register provides the N-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 0. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 0. See appendix B for a detailed description of the process used to derive the loop parameter values.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-43
XRC3
7 A & B
Dot Clock 0 Divisor Select Register
6 5 Post Divisor Select 4 3 Reserved 2 VCO Loop Divisor 1 Reserved 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to C3h shared by both pipelines A and B
Reserved
Note: All four of the registers used in specifying the loop parameters for dot clock 0 (XRC0 - XRC3) must be written, and in order from XRC0 to XRC3, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7 6-4 Reserved This bit always returns the value of 0 when read. Post Divisor Select These three bits select a value that specifies the post divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 0. The manner in which these bits are used to choose this value is shown in the table below:
Bits 654 000 001 010 011 100 101 110 111 Post Divisor 1 2 4 8 16 32 Reserved Reserved
A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 0. See the appendix B for a detailed description of the process used to derive the loop parameter values.
efmp69030 Databook
Revision 1.3 11/24/99
14-44 3 2
Extension Registers Reserved This bit always returns the value of 0 when read. VCO Loop Divisor Select This bit selects a value that specifies the VCO loop divide, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 0. 0: Selects a VCO loop divide value of 4. 1: Selects a VCO loop divide value of 1. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 0. See appendix B for a detailed description of the process used to derive the loop parameter values.
1-0
Reserved These bits always return the value 0 when read.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-45
XRC4
7 A & B
Dot Clock 1 VCO M-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to C4h shared by both pipelines A and B
Dot Clock 1 VCO M-Divisor
Note: All four of the registers used in specifying the loop parameters for dot clock 1 (XRC4 - XRC7) must be written, and in order, from XRC4 to XRC7 before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Dot Clock 1 VCO M-Divisor This register the M-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 1. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 1. See appendix B for a detailed description of the process used to derive the loop parameter values.
XRC5
7 A & B
Dot Clock 1 VCO N-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to C5h shared by both pipelines A and B
Dot Clock 1 VCO N-Divisor Bits 7-0
Note: All four of the registers used in specifying the loop parameters for dot clock 1 (XRC4 - XRC7) must be written, and in order from XRC4 to XRC7, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Dot Clock 1 VCO N-Divisor Bits 7-0 This register provides the N-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 1. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 1. See appendix B for a detailed description of the process used to derive the loop parameter values.
efmp69030 Databook
Revision 1.3 11/24/99
14-46
Extension Registers
XRC7
7 A & B
Dot Clock 1 Divisor Select Register
6 5 Post Divisor Select 4 3 Reserved 2 VCO Loop Divisor 1 Reserved 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to Index C7h shared by both pipelines A and B
Reserved
Note: All four of the registers used in specifying the loop parameters for dot clock 1 (XRC4 - XRC7) must be written, and in order from XRC4 to XRC7, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7 6-4 Reserved This bit always returns the value of 0 when read. Post Divisor Select These three bits select a value that specifies the post divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 1. The manner in which these bits are used to choose this value is shown in the table below:
Bits 654 000 001 010 011 100 101 110 111 Post Divisor 1 2 4 8 16 32 Reserved Reserved
A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 0. See appendix B for a detailed description of the process used to derive the loop parameter values.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers 3 2 Reserved This bit always returns the value of 0 when read.
14-47
VCO Loop Divisor Select This bit selects a value that specifies the VCO loop divide, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 1. 0: Selects a VCO loop divide value of 4. 1: Selects a VCO loop divide value of 1. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 1. See appendix B for a detailed description of the process used to derive the loop parameter values.
1-0
Reserved These bits always return the value 0 when read.
efmp69030 Databook
Revision 1.3 11/24/99
14-48
Extension Registers
XRC8
7 A B
Dot Clock 2 VCO M-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to C8h shadowed for pipelines A and B
Dot Clock 2 VCO M-Divisor Dot Clock 2 VCO M-Divisor
Note: All four of the registers used in specifying the loop parameters for dot clock 2 (XRC8 - XRCB) must be written, and in order from XRC8 to XRCB, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Dot Clock 2 VCO M-Divisor This register provides the M-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 2. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 2. See appendix B for a detailed description of the process used to derive the loop parameter values.
XRC9
7 A B
Dot Clock 2 VCO N-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to C9h shadowed for pipelines A and B
Dot Clock 2 VCO N-Divisor Dot Clock 2 VCO N-Divisor
Note: All four of the registers used in specifying the loop parameters for dot clock 2 (XRC8 - XRCB) must be written, and in order from XRC8 to XRCB, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Dot Clock 2 VCO N-Divisor Bits 7-0 This register provides the N-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 2. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 2. See appendix B for a detailed description of the process used to derive the loop parameter values.
efmp69030 Databook
Revision 1.3 11/24/99
Extension Registers
14-49
XRCB
7 A B Reserved Reserved
Dot Clock 2 Divisor Select Register
6 5 Post Divisor Select Post Divisor Select 4 3 Reserved Reserved 2 VCO Loop Divisor VCO Loop Divisor 1 Reserved Reserved 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to CBh shadowed for pipelines A and B
Note: All four of the registers used in specifying the loop parameters for dot clock 2 (XRC8 - XRCB) must be written, and in order from XRC8 to XRCB, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7 6-4 Reserved This bit always returns the value of 0 when read. Post Divisor Select These three bits select a value that specifies the post divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 2. The manner in which these bits are used to choose this value is shown in the table below:
Bits 654 000 001 010 011 100 101 110 111 Post Divisor 1 2 4 8 16 32 Reserved Reserved
A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 2. See appendix B for a detailed description of the process used to derive the loop parameter values.
efmp69030 Databook
Revision 1.3 11/24/99
14-50 3 2
Extension Registers Reserved This bit always returns the value of 0 when read. VCO Loop Divisor Select This bit selects a value that specifies the VCO loop divide, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate dot clock 2. 0: Selects a VCO loop divide value of 4. 1: Selects a VCO loop divide value of 1. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate dot clock 2. See appendix B for a detailed description of the process used to derive the loop parameter values.
1-0
Reserved These bits always return the value of 0 when read.
efmp69030 Databook
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Extension Registers
14-51
XRCC
7 A & B
Memory Clock VCO M-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to CCh shared by both pipelines A and B
Memory Clock VCO M-Divisor
Note: All three of the registers used in specifying the loop parameters for the memory clock (XRCC XRCE) must be written, and in order from XRCC to XRCE, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Memory Clock VCO M-Divisor These eight bits specify the M-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate the memory clock. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate the memory clock. See appendix B for a detailed description of the process used to derive the loop parameter values.
XRCD
7 A & B
Memory Clock VCO N-Divisor Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to CDh shared by both pipelines A and B
Memory Clock VCO N-Divisor
Note: All three of the registers used in specifying the loop parameters for the memory clock (XRCC XRCE) must be written, and in order from XRCC to XRCE, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7-0 Memory Clock VCO N-Divisor These eight bits specify the N-divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate the memory clock. A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate the memory clock. See appendix B for a detailed description of the process used to derive the loop parameter values.
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14-52
Extension Registers
XRCE
7 A & B
Memory Clock Divisor Select Register
6 5 Post Divisor Select 4 3 2 Reserved 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to CEh shared by both pipelines A and B
Memory Clock Select
Note: Before any value is written to bits other than bit 7 of register, bit 7 of this register should be set to 0 to select the default memory clock. Note: All three of the registers used in specifying the loop parameters for the memory clock (XRCC XRCE) must be written, and in order from XRCC to XRCE, before the hardware will update the synthesizer's settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer's output as new values are being written to these registers. 7 Memory Clock Select 0: The memory clock output is set to a preset frequency of 25.17540.00MHz. This is the default after reset. 1: The memory clock output is controlled by the loop parameters given to the memory clock synthesizer using a group of three registers (XRCC-XRCE) which includes this one. Post Divisor Select These three bits select a value that specifies the post divisor, one of the loop parameters used in controlling the frequency of the output of the synthesizer used to generate the memory clock. The manner in which these bits are used to choose this value is shown in the table below:
Bits 654 000 001 010 011 100 101 110 111 Post Divisor 1 2 4 8 16 32 Reserved Reserved
6-4
A series of calculations are used to derive this value and the values for the other loop parameters given a desired output frequency and a series of constraints placed on different components within the synthesizer used to generate the memory clock. See the appendix on clock generation for a detailed description of the process used to derive the loop parameter values. 3-0 Reserved These bits always return the value of 0 when read.
efmp69030 Databook
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Extension Registers
14-53
XRCF
7 A & B
Clock Configuration Register
6 Reserved (0000) 5 4 3 Power Seq Ref Clock (0) 2 Dot Clock Source (x) 1 Mem Clk Source (x) 0 Reserved (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to CFh shared by both pipelines A and B
Note: The default values of some of the bits of this register are determined by the settings of some of the strapping pins at reset. 7-4 3 Reserved These bits always return the value of 0 when read. Power Sequencing Reference Clock Select 0: The clock used to time the steps of panel powerdown or powerup is the reference input clock divided by 384. Presuming that the reference clock is the usual 14.31818MHz, the frequency resulting from this division should be 37.5KHz. This is the default after reset. 1: The clock used to time the steps of panel powerdown or powerup is the 32KHz clock provided as an input on one of the GPIO pins. This same clock is usually also used to provide a time base for memory refreshes during standby mode. Dot Clock Source 0: An external clock source received through the DCLKIN pin is used to provide the dot clock. All three of the synthesizers otherwise used to generate the three selectable dot clocks are disabled. 1: The three synthesizers used to generate the three selectable dot clocks are enabled. Note: The default state of this bit reflects the state of pin CFG_4 during reset. The state of pin CFG_4 during reset is also readable via bit 4 of the Configuration Pins 0 Register (XR70). Bit 4 of XR70 is read-only, while this bit is writable, allowing the source of the dot clock to be changed after reset. 1 Memory Clock Source 0: An external clock source is used to provide the memory clock. The synthesizer otherwise used to generate the memory clock is disabled. The graphics controller is configured to receive this external clock source on either one of two pins depending on the state of pin CFG_4 during reset. If CFG_4 was pulled low by an external pull-down resistor during reset, then the graphics controller will be configured to receive the external clock on the MCLKIN pin. If CFG_4 was allowed to be pulled high by the internal pull-up resistor during reset, then the graphics controller is configured to receive the MCLK/DCLK from the internal clock synthesizer. 1: The synthesizer used to generate memory clock is enabled. Note: The default state of this bit reflects the state of pin CFG_4 during reset. The state of pin CFG_4 during reset is also readable via bit 4 of the Configuration Pins 0 Register (XR70). Bit 4 of XR70 is read-only, while this bit is writable, allowing the source of the memory clock to be changed after reset. 0 Reserved This bit always returns the value of 0 when read.
2
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14-54
Extension Registers
XRD0
7 A
Reserved
Powerdown Control Register
6
Video Port Enable
read/write at I/O address 3D7h with index at I/O address 3D6h set to D0h partially shared and partially shadowed for pipelines A and B
5
Capture Enable
4
Pipeline A Playback En (1) Pipeline B Playback En (1)
3
MCLK VCO Enable
2
Pipe A DCLK VCO En (1) Pipe B DCLK VCO En (1)
1
Pipeline A Palette En (1) Pipeline B Palette En (1)
0
CRT Output Enable Status
B
(0)
(0)
(1)
(1)
(1)
7 Reserved This bit always returns the value of 0 when read. 6 Video Data Port Enable 0: Disables the video data port. This is the default after reset. 1: Enables the video data port. Video Data Capture Function Enable 0: Disables the capturing of video data. 1: Enables the capturing of video data. This is the default after reset. Video Data Playback Function Enable 0: Disables the playback of video data on a given pipeline. 1: Enables the playback of video data on a given pipeline. This is the default after reset. Memory Clock VCO Enable 0: Disables the memory clock VCO. 1: Enables the memory clock VCO. This is the default after reset. Dot Clock VCO Enable 0: Disables the dot clock VCO on a given pipeline. 1: Enables the dot clock VCO on a given pipeline. This is the default after reset. Palette Enable 0: Disables the palette on a given pipeline. 1: Enables the palette on a given pipeline. This is the default after reset. CRT Output Enable Status Note: This bit is read-only. This bit reflects the current state of bit 4 of FR02. It is provided only for compatibility with older software. Writes to this bit will be ignored. 0: At least the D-to-A converters of the CRT output have been disabled via bit 4 of FR02. Depending on the state of bit 4 of FR06, the HSYNC and VSYNC outputs may also have been tri-stated. 1: The CRT output has NOT been disabled via bit 4 of FR02.
5
4
3
2
1
0
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Extension Registers
14-55
XRD1
7 A & B
Power Conservation Control Register
6 5 4 Reserved (0000:000) 3 2 1 0 BitBLT Idle Powerdown (0)
read/write at I/O address 3D7h with index at I/O address 3D6h set to D1h shared by both pipelines A and B
7-1 0
Reserved This bit always returns the value of 0 when read. BitBLT Engine Idle-State Powerdown 0: Does not cause the BitBLT engine to automatically powerdown when idle. 1: Causes the BitBLT engine to automatically powerdown when idle. Note: Use of this feature in no way affects usability of the BitBLT engine, and in no way impedes access to the BitBLT registers. The manner in which the BitBLT engine is programmed is not affected by the use of this feature.
XRD2
7 A & B
2KHz Down Counter Register
6 5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to D2h shared by both pipelines A and B
32KHz Down Counter (00h)
7-0
2KHz Down Counter This register provides the output of a looping 8-bit counter that is continuously deincremented at a rate of 2KHz. The 2KHz frequency is derived from the same 14.318MHz reference frequency received from an external oscillator that is used as the base frequency for the generation of both the dot clock and memory clock. This register is meant to be used to provide a fixed time base that can be used by Intel BIOS to properly time the various steps to perform a powerdown or powerup of the graphics controller.
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14-56
Extension Registers
XRE0-XRE3
7 A B 6
Software Flag Registers
5 4 3 2 1 0
read/write at I/O address 3D7h with 3D6h set to indexes E0h to E3h shadowed for pipelines A and B
Pipeline A Software Flag Bits (xxxx:xxxx) Pipeline B Software Flag Bits (xxxx:xxxx)
7-0
Software Flag Bits The bits in each of these eight registers are used largely as a "scratch pad" by Intel BIOS. To a limited extent, these registers are also used as a medium of communication between Intel BIOS and Intel device drivers for various operating system environments and should not be accessed for any other purpose.
XRE4-XREF
7 A & B 6
Software Flag Registers
5 4 3 2 1 0
read/write at I/O address 3D7h with 3D6h set to indexes E4h to EFh shared by both pipelines A and B
Shared Software Flag Bits (xxxx:xxxx)
7-0
Software Flag Bits The bits in each of these eight registers are used largely as a "scratch pad" by Intel BIOS. To a limited extent, these registers are also used as a medium of communication between Intel BIOS and Intel device drivers for various operating system environments and should not be accessed for any other purpose.
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Extension Registers
14-57
XRF8-XRFC
7 A & B 6
Test Registers
5 4 3 2 1 0
read/write at I/O address 3D7h with index at I/O address 3D6h set to F8h to FCh shared by both pipelines A and B
Test Register Bits (xxxx:xxxx)
7-0
Test Register Bits The bits in each of these registers are used to perform chip testing, and should never be written to.
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Extension Registers
This page is intentionally left Blank.
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Flat Panel Registers
15-1
Chapter 15 Flat Panel Registers
Introduction
Chapter 15 describes the Flat Panel Registers for the 69030 Dual HiQVideo Accelerator. Table 15-1:
Name FR00 FR01 FR02 FR03 FR04 FR05 FR06 FR08 FR0A FR0B FR0C FR0F FR10 FR11 FR12 FR13 FR16 FR17 FR18 FR19 FR1A FR1E FR1F FR20 FR21 FR22 FR23 FR24 FR25 FR26 FR27 FR30 FR31 FR32 FR33 FR34 FR35 FR36 FR37 FR40 FR41 FR48 FR49-4C FR4D FR4E
Flat Panel Registers
Register Function Pipeline Feature Register (shadowed) Pipeline Enabling & Timing Select Register (shadowed) Output Enable & Assignment Register (shared) Output Blanking Register (shared) Panel Power Sequencing Delay Register Miscellaneous Control Register Output Disable State Register FP Pin Polarity Register Programmable Output Drive Register FP Pin Control 1 Register Pin Control 2 Register Activity Timer Control Register FP Format 0 Register FP Format 1 Register FP Format 2 Register FP Format 3 Register FRC Option Select Register Polynomial FRC Control Register FP Text Mode Control Register Blink Rate Control Register STN-DD Buffering Control Register M (ACDCLK) Control Register Diagnostic Register FP Horizontal Panel Display Size LSB Register FP Horizontal Sync Start LSB Register FP Horizontal Sync End Register FP Horizontal Total LSB Register FP HSync (LP) Delay LSB Register FP Horizontal Overflow 1 Register FP Horizontal Overflow 2 Register FP HSync (LP) Width and Disable Register FP Vertical Panel Size LSB Register FP Vertical Sync Start LSB Register FP Vertical Sync End Register FP Vertical Total LSB Register FP VSync (FLM) Delay LSB Register FP Vertical Overflow 1 Register FP Vertical Overflow 2 Register FP VSync (FLM) Disable Register Horizontal Compensation Register Horizontal Stretching Register Vertical Compensation Register Text Mode Vertical Stretching Register Vertical Line Replication Register Selective Vertical Stretching Disable Register Access Via Port 3D1h Index Value Port 3D0h 00h 01h 02h 03h 04h 05h 06h 08h 0Ah 0Bh 0Ch 0Fh 10h 11h 12h 13h 16h 17h 18h 19h 1Ah 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 30h 31h 32h 33h 34h 35h 36h 37h 40h 41h 48h 49h-4Ch 4Dh 4Eh
read-only read/write
read/write
read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write
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15-2 Table 15-1:
FR70 FR71 FR72 FR73 FR74
Flat Panel Registers Flat Panel Registers (Continued)
TMED Red Seed Register TMED Green Seed Register TMED Blue Seed Register TMED Control Register TMED2 Shift Control Register
read/write read/write read/write read/write read/write
70h 71h 72h 73h 74h
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Flat Panel Registers
15-3
FR00
7
Pipeline Feature Register
6
Reserved
read-only at I/O address 3D1h with 3D0h set to index 00h shadowed for pipeline A and B
5
Direct FP Interface (1) Direct FP Interface (0)
4
CRT Output (1) CRT Output (1)
3
Reserved (00) Reserved (00)
2
1
Hardware Popup (0) Hardware Popup (1)
0
Hardware Cursor (1) Hardware Cursor (1)
A (00) Reserved B (00)
Note: This register should be read by all user-installable software as a way to confirm the feature set available on each pipeline. 7-6 5 Reserved These bits always return the value of 0 when read. Direct Flat Panel Interface Output Availability For pipeline A: This bit always returns the value of 1, indicating that the flat panel interface IS available on pipeline A as an output. For pipeline B: This bit always returns the value of 0, indicating that the flat panel interface is NOT available on pipeline B as an output. 4 CRT Output Availability This bit always returns the value of 1 for both pipelines, indicating that the CRT DAC and sync outputs are available on either pipeline as an output. Reserved These bits always return the value of 0 when read. Hardware Popup Availability For pipeline A: This bit always returns the value of 1, indicating that there IS a hardware popup on pipeline A. For pipeline B: This bit always returns the value of 0, indicating that there is NO hardware popup on pipeline B. 0 Hardware Cursor Availability This bit always returns the value of 1 for both pipelines, indicating that the each pipeline has a hardware cursor.
3-2 1
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15-4
Flat Panel Registers
FR01
7 A B
Pipeline Enable & Timing Select Register
6 Reserved (0000) Reserved (0000:00) 5 4 3 2 1 0
read/write at I/O address 3D1h with 3D0h set to index 01h shadowed for pipeline A and B
DCLK Select (10) Pipe A En & Timing Sel (01) Pipe B En & Timing Sel (01)
7-4 3-2
Reserved These bits always return the value of 0 when read. DCLK Select / Reserved For pipeline A: If bits 1 and 0 of pipeline A's shadow of this register are set such that pipeline A is enabled, and timing registers OTHER THAN the CR timing registers have been selected for timing control, then these 2 bits are used to select the dot clock, and bits 3 and 2 of MSR for the given pipeline are ignored. However, if bits 1 and 0 of pipeline A's shadow of this register are set such that the given pipeline is enabled, and the CR timing registers have been selected for timing control, then bits 3 and 2 of MSR are used to select the dot clock, and these 2 bits for the given pipeline are ignored. Bits 32 00 01 10 11 DCLK0 DCLK1 DCLK2 - This is the default after reset. reserved Dot Clock Synthesizer Selected
For pipeline B: These bits are reserved and always return a value of 0 when read.
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Flat Panel Registers 1-0 Pipeline Enable and Timing Register Select
15-5
These two bits are used to enable the pipelines (including the basic function of scanning on-screen data from the frame buffer to the screen), and selecting the timing registers that should be used (in the case of pipeline A, which can use either CR or FR timing register sets). Bits 10 00 Pipeline Enable/Disable and Timing Register Set Selected For both pipelines: Pipeline disabled and no timing register set selected for use, though all registers and memory locations remain accessible by the host CPU. No on-screen data is scanned from the frame buffer to the display assigned to this pipeline. This is the default after reset. For both pipelines: Pipeline enabled and CR timing registers selected for timing control. Bits 3 and 2 of MSR select the dot clock. 10 For pipeline A: Pipeline enabled and FR timing registers selected for timing control. Bits 3 and 2 of this register select the dot clock. For pipeline B: Reserved. Pipeline disabled and no timing register set selected for use, though all registers and memory locations remain accessible by the host CPU. No on-screen data is scanned from the frame buffer to the display assigned to this pipeline. 11 For both pipelines: Reserved. Pipeline disabled and no timing register set selected for use, though all registers and memory locations remain accessible by the host CPU. No on-screen data is scanned from the frame buffer to the display assigned to either pipeline.
01
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15-6
Flat Panel Registers
FR02
7 A & B
Output Enable & Assignment Register
6 Reserved (00) 5 Direct FP Interface En (0) 4 CRT Output En (0) 3 2 Reserved (000) 1 0 CRT Out Assign (0)
read/write at I/O address 3D1h with 3D0h set to index 02h shared by both pipelines A and B
7-6 5
Reserved These bits always return the value of 0 when read. Direct Flat Panel Interface Output Enable 0: The flat panel interface is disabled. All flat panel output signals are either tri-stated with weak internal pull-down resistors or driven inactive, depending on the setting of bit 1 of FR06. In this state, it is safe to connect/disconnect flat panels to the flat panel interface. This is the default after reset, but if this bit is set to 0 after having been set to 1, then the flat panel power-down sequence takes place. 1: The flat panel interface is enabled. All flat panel output signals are driven, and in this state, it is NOT safe to connect/disconnect flat panels to the flat panel interface. When this bit is set to 1 after having been set to 0, the panel power-up sequence takes place. CRT Output Enable 0: The CRT output is disabled. All D-to-A converters are disabled. The HSYNC and VSYNC outputs either continue to be driven or are tri-stated depending on the setting of bit 4 of FR06. While disabled, the CRT output may be reassigned from one pipeline to another using bit 0 of this register. This is the default after reset. 1: The CRT output is enabled. All D-to-A converters are enabled, and the HSYNC and VSYNC outputs are driven. While enabled, the CRT output should NEVER be reassigned from one pipeline to another. Note: The state of this bit is also readable from bit 0 of XRD0.
4
3-1 0
Reserved These bits always return the value of 0 when read. CRT Output Assign 0: The CRT DAC and sync outputs are driven by pipeline A. This is the default after reset. 1: The CRT DAC and sync outputs are driven by pipeline B. Important: Bit 4 of this register MUST be used to disable the CRT output BEFORE it is switched from being driven by one pipeline to being driven by the other.
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Flat Panel Registers
15-7
FR03
7 A & B
Output Blanking Register
6 Reserved (00) 5 Direct FP I/F Blnk (0) 4 3 2 Reserved (0:0000) 1 0
read/write at I/O address 3D1h with 3D0h set to index 03h shared by both pipelines A and B
7-6 5
Reserved These bits always return the value of 0 when read. Direct Flat Panel Interface Output Blank 0: The flat panel interface can be driven with on-screen data scanned from the frame buffer, as usual. This is the default after reset. 1: The flat panel interface is driven with nothing but zeros for data, causing the output data to be nothing but zeros, thereby blanking the image on the flat panel. This has no effect on timing signals sent to the flat panel and has nothing to do with powering down the flat panel, i.e., LP and FLM remain unaffected. Reserved These bits always return the value of 0 when read.
4-0
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15-8
Flat Panel Registers
FR04
7 A B
Panel Power Sequencing Delay Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 04h shared by both pipelines A and B
Power Up Delay (1000) not shadowed for this pipeline Power Down Delay (0001)
This register controls panel power on/off sequencing delays. The generation of the clock for the panel power sequencing logic is controlled by XRCF bit 3. The delay intervals above assume a 37.5 KHz clock generated by the 14.31818 MHz reference clock. If using a 32KHz input, scale the delay intervals accordingly. 7-4 Power Up Delay Programmable value of panel power sequencing during power up. This value can be programmed up to 54 milliseconds in increments of 3.4 milliseconds. A value of 0 is undefined. Power Down Delay Programmable value of panel power-sequencing during power down. This value can be programmed up to 459 milliseconds in increments of 27.5 milliseconds. A value 0 is undefined.
3-0
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Flat Panel Registers
15-9
FR05
7 A & B
Miscellaneous Control Register
6 Reserved (000) 5 4 Host I/F Disable (0) 3 Screen Refresh Dis (0) 2 1 Normal Refresh Count (000) 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 05h shared by both pipelines A and B
7-5 4
Reserved These bits always return the value of 0 when read. Host Interface Disable 0: The host interface is enabled and functions normally. All registers and memory locations are accessible by the host CPU as usual. This is the default after reset. 1: The host interface is disabled. All registers and memory locations become inaccessible to the host CPU, and all pins of the host interface are ignored except for the RESET# pin. The host interface can be re-enabled (and this bit cleared to 0, as a result) only by a hardware reset via the RESET# pin or a low-to-high transition on the STNDBY# pin. Screen Refresh Disable 0: Screen refresh enabled for both pipelines, i.e, normal operation. This is the default after reset. 1: Screen refresh disabled for both pipelines. In other words, no on-screen image data is being scanned out of the frame buffer for either pipeline. The frame buffer and all graphics controller registers remain accessible. Normal Refresh Count These bits specify the number of memory refresh cycles per scanline. However, there is guaranteed a minimum of 1 refresh cycle per scanline regardless of whether these bits are set to 001 or 000.
3
2-0
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15-10
Flat Panel Registers
FR06
7 A & B
Output Disable State Register
6 Reserved (000) 5 4 CRT Sync Dis State (0) 3 Reserved (00) 2 1 Direct FP DIS State (0) 0 Reserved (0)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 06h shared by both pipelines A and B
7-5 4
Reserved These bits always return the value of 0 when read. CRT Output Sync Disable State 0: Whenever the CRT output is disabled, as by the use of bit 4 of FR02 or the STNDBY# pin, the HSYNC and VSYNC output pins are tri-stated. This is the default after reset. 1: Whenever the CRT output is disabled, as by the use of bit 4 of FR02 or the STNDBY# pin, the HSYNC and VSYNC output pins are allowed to remain active. Reserved These bits always return the value of 0 when read. Direct Flat Panel Interface Disable State 0: Whenever the flat panel interface is disabled, as by the use of bit 5 of FR02 or the STNDBY# pin, all flat panel output signals are tri-stated with weak internal pull-down resistors. This is the default after reset. 1: Whenever the flat panel interface is disabled, as by the use of bit 5 of FR02 or the STNDBY# pin, all flat panel output signals are driven inactive. Reserved This bit always returns the value of 0 when read.
3-2 1
0
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Flat Panel Registers
15-11
FR08
7 A B
FP Pin Polarity Register
6 Alt HSYNC Polarity (0) 5 FP Graphics Polarity (0) 4 FP Text Polarity (0) 3 FLM Polarity (0) 2 LP Polarity (0) 1 Disp Enbl Polarity (0) 0 Reserved (R/W) (0)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 08h shadowed only for pipeline A
Alt VSYNC Polarity (0)
not shadowed for this pipeline
7
Alternate CRT VSync Polarity This bit is used instead of MSR bit 7 when not in CRT mode (when FR01 bit 0 is set to 0). 0: Positive polarity (default) 1: Negative polarity Alternate CRT HSync Polarity This bit is used instead of MSR bit 6 when not in CRT mode (when FR01 bit 0 is set to 0). 0: Positive polarity (default) 1: Negative polarity FP Graphics Video Output Polarity This bit affects FP video data output in graphics mode only. 0: Normal polarity (default) 1: Inverted polarity FP Text Video Output Polarity This bit affects FP video data output in text mode only. 0: Normal polarity (default) 1: Inverted polarity FP VSync (FLM) Polarity 0: Positive polarity (default) 1: Negative polarity FP HSync (LP) Polarity 0: Positive polarity (default) 1: Negative polarity FP Display Enable Polarity 0: Positive polarity (default) 1: Negative polarity Reserved (R/W)
6
5
4
3
2
1
0
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15-12
Flat Panel Registers
FR0A
7 A B
Programmable Output Drive Register
6 HS, VS & ACTI (0) 5 Reserved (Writable) (0) 4 Mem Ctrl & Data (0) 3 Bus Output Drive (0) 2 FP Output Drive (0) 1 Reserved (Writable) (0) 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 0Ah shadowed only for pipeline A
Mem Addr Drive (0)
not shadowed for this pipeline
Note: This register controls the input threshold and output drive of the bus, video and memory interface pins. 7 Memory Interface Address Output Drive Select 0: Lower drive (Default) 1: Higher drive HSYNC, VSYNC, ACTI and PCLK output drive select 0 0: Lower drive (Default) 1: Higher drive Reserved (Writable) This bit should always be set to the value of 0. Memory Interface Control and Data Output Drive Select 0: Lower drive (Default) 1: Higher drive Bus Interface Output Drive Select 0: Higher drive (Default) 1: Lower drive Flat Panel Interface Output Drive Select 0: Lower drive (Default) 1: Higher drive Reserved (Writable) These bits should always be set to the value of 0.
6
5 4
3
2
1-0
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Flat Panel Registers
15-13
FR0B
7
FP Pin Control 1 Register
6 Reserved 5 Comp Sync (00) (0) 4 Reserved 3 Pins W4 & U6 Select (0) 2 Pins U3 & V2 Select (0) 1 Pin Y4 Select (0) 0 Pin V6 Select (0)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 0Bh shadowed only for pipeline A
A B
not shadowed for this pipeline
7-6 5
Reserved (writable) These bits should always be written with the value of 0. Simple Composite Sync 0: Output CRT HSYNC on pin U3. 1: Output CRT HSYNC ORed with CRT VSYNC on pin U3. Effective only when XR0B bit 2 is set to 0. Reserved (0) Pin W4 and Pin U6 Select 0: Enable VEE (ENAVEE) goes to pin W4. Enable Backlight (ENABKL) goes to pin U6. (default). 1: Enable VEE (ENAVEE) goes to pin U6. Enable Backlight (ENABKL) goes to pin U6. Pin U3 and Pin V2 Select 0: CRT HSync signal goes to pin U3. CRT VSync signal goes to pin V2. (default) 1: Composite Sync (CSYNC) goes to pin U3. Modified VSync signal goes to pin V2. Pin Y4 Select 0: FP HSync (LP) signal goes to pin Y4 (default) 1: FP Display Enable (FP Blank#) goes to pin Y4. Pin V6 Select 0: FP "M" signal goes to pin V6 (default) 1: FP Display Enable (FP Blank#) goes to pin V6.
4 3
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
15-14
Flat Panel Registers
FR0C
7 A
Pin Control 2 Register
6 5 Reserved (R/W) (0) 4 3 2 1 Reserved (R/W) (000) 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 0Ch shadowed only for pipeline A
GPIO Pin Control (00) B GPIO (ACTI) (00) not shadowed for this pipeline
7-6
GPIO1 (C32KHz) Pin Control
Bits 76 00 01 10 11
GPIO1 (C32KHz) Pin Control Pin T4 is C32KHz input (default). Also see XRCF Bit 3 Reserved Pin T4 is general purpose input 1 (GPIO1). Data is read into XR63 Bit 1 Pin T4 is general purpose output 1 (GPIO1). Data comes from XR63 Bit 1
5 4-3
Reserved (R/W) GPIO0 (ACTI) Pin Control
Bits 43 00 01 10 11
GPIO0 (ACTI) Pin Control Pin V1 is ACTI output (default) Pin V1 is Composite Sync output Pin V1 is general purpose input 0 (GPIO0). Data is read into XR63 Bit 0 Pin V1 is general purpose output 0 (GPIO0). Data comes from XR63 Bit 0
2-0
Reserved (R/W)
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-15
FR0F
7 A B Activity Timer (0)
Activity Timer Control Register
6 Timer Action 5 Reserved (R/W) 4 3 2 Activity Timer Count not shadowed for this pipeline 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 0Fh shadowed only for pipeline A
Note: This register controls the activity timer functions. The activity timer is an internal counter that starts from a value programmed into this register (see bits 0-4 below) and is reset back to that count by read or write accesses to graphics memory or standard VGA I/O. Reading or writing extended VGA registers does not reset the counter. If no accesses occur, the counter increments until the end of its programmed interval then activates either the ENABKL pin or Panel Off mode (as selected by bit-6 below). The timer count does not need to be reloaded once programmed and the timer enabled. Any access to the chip with the timer timed out (ENABKL active or Panel Off mode active) resets the timer and deactivates the ENABKL (or Panel Off mode) pin. The activity timer uses the same clock as the power sequencing logic. The delay intervals assume a 37.5 KHz clock. If using a 32KHz input, scale the delay intervals accordingly. 7 Enable Activity Timer 0: Disable activity timer (default on reset) 1: Enable activity timer Activity Timer Action 0: When the activity timer count is reached, the ENABKL pin is activated (driven low to turn the backlight off) 1: When the activity timer count is reached, Panel Off mode is entered. Reserved (R/W) Activity Timer Count For a 37.5KHz power sequencing clock, the counter resolution is 28.1 seconds. The minimum programmed value of 0 results in 28.1 seconds delay, and the maximum value of 1Eh results in a delay of 15 minutes.
6
5 4-0
efmp69030 Databook
Revision 1.3 11/24/99
15-16
Flat Panel Registers
FR10
7 A B
FP Format 0 Register
6 5 Shift Clock Divide (000) 4 3 2 1 Panel Type (00) 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 10h shadowed only for pipeline A
Reserved (R/W) (0) Mono / Color (00) not shadowed for this pipeline
7 6-4 .
Reserved (R/W) (reset state: 0) Shift Clock Divide (reset state: 000) These bits specify the frequency ratio between the internal dot clock (DCLK) and flat panel shift clock (SHFCLK) signal.
Color TFT Pixel / SHFCLK SHFCLK DCLK 1 DCLK/2 2 -- -- -- -- -- -- -- -- -- -- -- -- 4-bit pack Color STN-SS Pixel / SHFCLK SHFCLK DCLK 1 1/3 DCLK/2 2 2/3 DCLK/4 5 1/3 -- -- -- -- -- -- -- -- -- --
Bits [6-4] 000 001 010 011 100 101 110 111
Max bpp 24 12 -- -- -- -- -- --
Bits [6-4] 000 001 010 011 100 101 110 111
Max bpp 4 8 16 -- -- -- -- --
Monochrome STN-DD w/o frame accel. Bits Pixel / SHFCLK Max bpp [6-4] SHFCLK 000 DCLK 1 2 001 DCLK/2 2 4 010 DCLK/4 4 8 011 DCLK/8 8 16 100 -- -- -- 101 -- -- -- 110 -- -- -- 111 -- -- -- 4-bit pack color STN-DD w/frame accel. Bits Pixel / SHFCLK Max bpp [6-4] SHFCLK 000 DCLK 2 2/3 8 001 DCLK/2 5 1/3 16 010 -- -- -- 011 -- -- -- 100 -- -- -- 101 -- -- -- 110 -- -- -- 111 -- -- --
Monochrome STN-DD w/o frame accel. Bits Pixel / SHFCLK Max bpp [6-4] SHFCLK 000 -- -- -- 001 DCLK/2 2 2 010 DCLK/4 4 4 011 DCLK/8 8 8 100 DCLK/16 16 16 101 -- -- -- 110 -- -- -- 111 -- -- -- 4-bit pack color STN-DD w/o frame accel. Bits Pixel / SHFCLK Max bpp [6-4] SHFCLK 000 -- -- -- 001 DCLK/2 2 2/3 8 010 DCLK/4 5 1/3 16 011 -- -- -- 100 -- -- -- 101 -- -- -- 110 -- -- -- 111 -- -- --
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers 6-4 Shift Clock Divide (continued)
3-bit pack color STN-DD w/ frame accel. Bits Pixel / SHFCLK Max bpp [6-4] SHFCLK 000 DCLK 2 6 001 DCLK/2 4 12 010 DCLK/4 8 24 011 -- -- -- 100 -- -- -- 101 -- -- -- 110 -- -- -- 111 -- -- --
15-17
3-bit pack color STN-DD w/o frame accel. Bits Pixel / SHFCLK Max bpp [6-4] SHFCLK 000 -- -- -- 001 DCLK/2 2 6 010 DCLK/4 4 12 011 DCLK/8 8 24 100 -- -- -- 101 -- -- -- 110 -- -- -- 111 -- -- --
Monochrome TFT
Bits [6-4] 000 001 010 011 100 101 110 111 SHFCLK DCLK DCLK/2 DCLK/4 DCLK/8 DCLK/16 -- -- -- Pixel/SHFCLK 1 2 4 8 16 -- -- -- Max bpp 8 8 4 2 1 -- -- --
3-2
Panel Monochrome/Color Select
Bits 32 00 01 10 11
Panel Monochrome/Color Select
Monochrome panel: NTSC weighting color reduction algorithm (default) Monochrome panel: Equivalent weighting color reduction algorithm Monochrome panel: Green only color reduction algorithm Color panel
For monochrome panels, these bits select the algorithm used to reduce 18 and 24-bit color data to 6 and 8-bit color data. 1-0 Panel Type
Bits 10 00 01 10 11
Panel Type Single Panel Single Drive (SS) (default) Reserved
Reserved
Dual Panel Dual Drive (DD)
efmp69030 Databook
Revision 1.3 11/24/99
15-18
Flat Panel Registers
FR11
7 A B
FP Format 1 Register
6 5 Bits Per Pixel (000) 4 3 2 1 FRC 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 11h shadowed only for pipeline A
Res Dither (0) Dither Enable
not shadowed for this pipeline
7
FP Restrict Dither (reset state: 0) 0: Dithering can be enabled on all modes. 1: Dithering can be enabled only on modes with more than 256 colors. Bits Per Pixel Select (reset state: 000) Gray/Color without dither
Bits [6-4] 000 001 010 011 100 101 110 111 #MSBs Used 0 1 2 3 4 5 6 8 No FRC -- 2 4 8 16 32 64 256 2-Frame FRC -- -- 3 5 15 31 -- -- 16 -- -- -- 16-Frame FRC -- Bits [6-4] 000 001 010 011 100 101 110 111
6-4
Gray/Color with dither
#MSBs Used 0 1 2 3 4 5 6 8 No FRC -- 5 13 29 61 125 253 2-Frame FRC -- -- 9 25 57 121 -- -- 61 -- -- -- 16-Frame FRC --
Notes: 1) No FRC is the recommended setting when interfacing with color TFT panel with more than 12 bits per pixel (4K color) or interfacing with monochrome panel with internal gray scaling. When No FRC is chosen FR11 bits 6-4 should be programmed equal to the number of bits/ color of the panel. For example, a TFT panel with 18 bits/pixel color uses 6 bits/color. FR11 bits 6-4 should be programmed to 110b. 2-frame FRC should be used with color TFT panel with less than or equal to 12 bits per pixel (<4k color) or used with monochrome panel with internal gray scaling. When 2-frame FRC is chosen FR11 bits 6-4 should be programmed equal to the number of bits/color of the panel plus 1. The extra bit is for the 2-frame FRC. For example, a TFT panel with 9 bits/pixel color uses 3 bits/color. FR11 bits 16-4 should be programmed equal to 100b. 16-frame FRC should be used with STN panel. To achieve 16-frame FRC, 4 bits are needed for each color (R, G, B). When 2-bit dither is disabled, the theoretical Color/Gray level per R, G, and B is calculated by using the formula below: Theoretical Color/Gray level = 2X where X is number of bits/color selected 5) When 2-frame FRC or 16-frame FRC is enabled the actual Color/Gray level per R, G, and B that can be achieved is less than the theoretical Color/Gray level. When 2-bit dither is enabled, the theoretical Color/Gray level per R, G, and B is calculated by using the formula below: Theoretical Color/Gray Level = 4 * 2X where X is number of bits/color selected
2)
3) 4)
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers 3-2
15-19
Dither Enable When 2-bit dither, 2-frame FRC, or 16-frame FRC is enabled the actual achievable Color/ Gray level per R, G, and B is less than the theoretical Color/Gray level. 3-2Dither Enable
Bits 32 00 01 10 11
Dither Enable Disable dithering (default) Enable 2-bit dithering Reserved for 4-bit dithering Reserved
1-0
Frame Rate Control (FRC) FRC is grayscale simulation on frame-by-frame basis to generate shades of gray or color on panels that do not generate gray/color levels internally.
Bits 10 00
Frame Rate Control (FRC) No FRC. This setting may be used with all panels, especially for panels which can generate shades of grey/color internally (default). 16-Frame FRC. This setting may be used for panels which do not support internal grayscaling such as color STN or monochrome STN panels. This setting simulates up to 16 gray/color levels per pixel as specified in FR11 Bits 6-4. 2-frame FRC. This setting may be used with color/ monochrome panels, especially for panels which can generate shades of gray/color internally. The valid number of bits/pixel is specified in FR11 Bits 6-4. 2-frame FRC. This setting may be used with color/ monochrome panels, especially for panels which can generate shades of gray/color internally. The valid number of bits/pixel is specified in FR11 Bits 6-4.
01
10
11
efmp69030 Databook
Revision 1.3 11/24/99
15-20
Flat Panel Registers
FR12
7 A
FP Format 2 Register
6 5 Force FP Data High 4 Force HSYNC 3 FP Blank# Select (0) 2 Clk Mask STN-DD (0) 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 12h shadowed only for pipeline A
FP Data Width (00) B Clock Mask Clock Divide (0) (0)
not shadowed for this pipeline
7-6
FP Data Width
Bits 76 00
FP Data Width 16-bit panel data width. For color TFT panel this is the 565 RGB interface. This is the default after reset. 24-bit panel data width. For color the TFT panel this is the 888 RGB interface. This setting can also be used for the 24bit color STN-DD panel. Reserved. 36-bit panel data width (TFT panels only). Program 000 in shift clock divide bits of FR10.
01 10 11
5
Force FP Data Signals High during Vertical Blank 0: Flat panel data output signals are not forced high during vertical blanking. 1: Flat panel data output signals are forced high during vertical blanking. Force FP HSync (LP) during Vertical Blank 0: FP Display Enable output is generated by inverting both FP Vertical and Horizontal Blank therefore FP Display Enable will not toggle active during Vertical Blank time. FP HSync (LP) is not generated during Vertical Blank except when bit 3 is set to 1. This is the default after reset. 1: FP Display Enable output is generated by inverting FP Horizontal Blank only therefore FP Display Enable will be active during Vertical Blank time. FP HSync (LP) will also be active during Vertical Blank. This bit should be set only for SS panels which require FP HSync (LP) to be active during vertical blank time when bit 3 is 0. This bit should be reset when using DD panels or when bit 3 is 1.
4
3
FP Display Enable (FP Blank#) Select 0: The FP Display Enable is inactive during vertical blank time because the output comes from inverting both the FP Vertical and Horizontal blank. FP HSync is not generated during vertical blank except when bit 4 is set to 1. In 480-line DD panels, this option will generate exactly 240 FP HSync (LP) pulses. This is the default after reset. 1: The FP Display Enable is active during Vertical blank time since the output comes from inverting the FP Horizontal Blank enable. FP HSync will also be active during vertical blank. This bit controls FP Display Enable (FP Blank#) generation. This bit also affects FP HSync (LP) generation.
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers 2
15-21
Shift Clock Mask for STN-DD 0: Allow Shift Clock output to toggle in first line of Vertical Blank. This is the default after reset. 1: Force Shift Clock output low in first line of Vertical Blank. This is an option to eliminate dark lines in the middle of STN-DD panels. Shift Clock Mask 0: Allow Shift Clock output to toggle outside the display enable interval. This is the default after reset. 1: Force Shift Clock output low outside the display enable interval. Shift Clock Divide 0: Shift Clock to Dot Clock relationship is specified by FR10 bits 6-4. This is the default after reset. 1: Shift Clock is further divided by 2 and different video data is valid on the rising and falling edges of Shift Clock.
1
0
efmp69030 Databook
Revision 1.3 11/24/99
15-22
Flat Panel Registers
FR13
7 A B
FP Format 3 Register
6 5 Reserved (R/W) (0000:0) 4 3 2 Set Up Time (0) 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 13h shadowed only for pipeline A
Pixel Packing (00)
not shadowed for this pipeline
7-3 2
Reserved (R/W) (reset state: 0000-0) Increase Setup Time 16-bit Color STN-DD 0: Normal data setup time with respect to SHFCLK falling edge (default). Maximum SHFCLK frequency is DCLK/2 (1:1 duty cycle). 1: Extended data setup time with respect to SHFCLK falling edge. The setup time is increased by approximately half of a dot clock cycle. This is done by extending SHFCLK high time by half of a dot clock cycle. Maximum SHFCLK frequency is DCLK/2.5 with a 1.5:1 duty cycle. This bit is effective only for 16-bit Color STN-DD when frame acceleration is enabled or for 8-bit Color STN-DD when frame acceleration is disabled.
1-0
Color STN Pixel Packing
Bits 10 00 01 10 11
Color STN Pixel Packing 3-bit pack (default). 4-bit pack. Reserved. Extended 4-bit pack. Bits FR10 Bits 6-4 must be programmed to 001. This setting may only be used for 8-bit interface color STN SS panels.
This determines the type of pixel packing (the RGB pixel output sequence) for color STN panels. These bits must be programmed to 00 for monochrome STN panels and for all TFT panels.
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-23
FR16
7 A B
FRC Option Select Register
6 5 Reserved (R/W) (0000:0) not shadowed for this pipeline 4 3 2 FRC Opt 3 (1) 1 FRC Opt 2 (1) 0 FRC Opt 1 (1)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 16h shadowed only for pipeline A
7-3 2
Reserved (R/W) These bits should always be written with 0's for future compatibility. FRC Option 3 This affects 2-frame FRC and normally should be set to 1. 0: FRC data changes every frame 1: FRC data changes every other frame FRC Option 2 This affects 16-frame FRC and normally should be set to 1. 0: 2x2 FRC sub-matrix 1: 2x4 FRC sub-matrix FRC Option 1 This affects 16-frame FRC and normally should be set to 1. 0: 15x31 FRC matrix 1: 16x32 FRC matrix
1
0
efmp69030 Databook
Revision 1.3 11/24/99
15-24
Flat Panel Registers
FR17
7 A B
Polynomial FRC Control Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 17h shadowed only for pipeline A
Polynomial M Value not shadowed for this pipeline Polynomial N Value
This register sets the FRC polynomial counters, which are row and column offsets for each panel type and are usually determined by trial and error. These values affect the quality of both 2-frame and the 16-frame FRC algorithms and require readjustment when the horizontal or vertical parameters change, especially when the vertical total parameter is changed. 7-4 3-0 Polynomial 'M' Value Polynomial 'N' Value
FR18
7 A B
FP Text Mode Control Register
6 5 Reserved (0000:00) not shadowed for this pipeline 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 18h shadowed only for pipeline A
Text Enhancement (00)
7-2 1-0
Reserved (0) Text Enhancement
Bits 10 00 01
Text Enhancement Normal text (default) Text attribute 07h and 0Fh are reversed to maximize the brightness of the normal DOS prompt. This affects both CRT and Flat Panel displays. Text attribute 07h and 0Fh are reversed to maximize the brightness of the normal DOS prompt. This affects Flat Panel displays. Reserved
10 11
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-25
FR19
7 A B
Blink Rate Control Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 19h shadowed only for pipeline A
Char Blink Duty Cycle (10) Cursor Blink Rate (00:0011) not shadowed for this pipeline
7-6
Character Blink Duty Cycle These bits specify the character blink (also called 'attribute blink') duty cycle in text mode.
Bits 76 00 01 10 11
Character Blink Duty Cycle 50% 25% 50% (default on reset) 75%
For setting 00, the character blink period is equal to the cursor blink period. For all other settings, the character blink period is twice the cursor blink period (character blink is half as fast as cursor blink). 5-0 Cursor Blink Rate (default = 03h) These bits specify the cursor blink period in terms of number of VSyncs (50% duty cycle). In text mode, the character blink period and duty cycle is controlled by bits 7-6 of this register. These bits should be programmed to: Programmed value = ((Actual Value) / 2) - 1 Note: In graphics mode, the pixel blink period is fixed at 32 VSyncs per cursor blink period with 50% duty cycle (16 on and 16 off).
efmp69030 Databook
Revision 1.3 11/24/99
15-26
Flat Panel Registers
FR1A
7 A
STN-DD Buffering Control Register
6 5 4 3 2 1 Frame Accel Enable (0) 0 Buffering Enable (0)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 1Ah shadowed only for pipeline A
Reserved (Writable) (0000:00) B not shadowed for this pipeline
7-2 1
Reserved (Writable) These bits should always be set to the value of 0. STN-DD Frame Acceleration Enable Enabling STN-DD frame acceleration doubles the screen refresh rate on an attached STNDD panel relative to an attached CRT (each CRT frame corresponds to two STN-DD panel frames). The required memory bandwidth does not increase. In the simultaneous display mode, if the CRT refresh rate is 60Hz, the STN-DD panel refresh rate is 120Hz when STNDD frame acceleration is enabled. Under the same conditions, the STN-DD panel refresh rate is 60Hz when STN-DD frame acceleration is disabled. Usually, STN-DD panels display higher quality images when STN-DD frame acceleration is enabled. If STN-DD frame acceleration is disabled, then the STN-DD buffer must be large enough to hold an entire frame consisting of 3-bits per pixel organized as 10 pixels per 32-bit Dword. With STN-DD frame acceleration enabled, the required STN-DD buffer size is half this amount (only half a frame need be stored). STN-DD Buffering Enable 0: Disables STN-DD buffering. This is the default after reset. 1: Enables STN-DD buffering. STN-DD buffering is required for STN-DD panel operation. For STN-SS panel operation, STN-DD buffering is not required so this bit must be set to 0.
0
FR1E
7 A B
M (ACDCLK) Control Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 1Eh shadowed only for pipeline A
ACDCLK Control M(ACDCLK) Count (ACDCNT) not shadowed for this pipeline
7
M (ACDCLK) Control 0: The M (ACDCLK) phase changes depending on bits 0-6 of this register 1: The M (ACDCLK) phase changes every frame if the frame accelerator is not used. If the frame accelerator is used, the M (ACDCLK) phase changes every other frame. This register is used only in flat panel mode. M (ACDCLK) Count (ACDCNT) These bits define the number of HSyncs between adjacent phase changes on the M (ACDCLK) output. These bits are effective only when bit 7 = 0 and the contents of this register are greater than 2. Programmed Value = Actual Value - 2
6-0
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-27
FR1F
7 A
Diagnostic Register
6 5 4 3 Misc Mod Control 2 (0) 2 Misc Mod Control 2 (0) 1 Bypass VGA Palette (0) 0 Diagnostic Mode (0)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 1Fh shadowed only for pipeline A
Reserved (R/W) (00) B Pixel Data Output Mode (00)
not shadowed for this pipeline
7-6 5-4
Reserved (R/W) (reset state: 00) Pixel Data Pin Diagnostic Output Mode These bits control the output of pins: SHFCLK, LP, M, P bits 15-0 and CA bits 7-0. 00: Normal Operation (default) 01: Output the following internal signals: Signal PDCLK RDDE RDBLANK RDVIDEO bits 23-16 RDVIDEO bits 15-0 Pins FLM LP M CA bits 7-0 P bits 15-0
10: Output the following internal signals on P bits 15-0
PDDELETE, PDGDCK, PHHSTR[2:0], PHREMAIN bits 10-0
11: Output the following internal signals on P bits 13-0
SS1ROMBOE, FHC32KHZI, FHXMEMRQ, T2DDSPBP, T2DDSPEN, T2DHBLANK, MXSQRDBG bits 7-0
3
FP Miscellaneous module control 2 0: Normal Operation. This is the default after reset. 1: Enable the ring oscillator. The waveform is output on ACTI pin. In addition, it is also output on pin A25 if the configuration option of pin AA4 is chosen to output clocks on A24 and A25. FP Miscellaneous module control 2 0: Normal Operation. This is the default after reset. 1: Bypass clock divider for testing purposes. Bypass VGA Palette 0: Normal Operation. This is the default after reset. 1: Bypass internal VGA palette. FP Interface Diagnostic Mode 0: Normal Operation. This is the default after reset. 1: FP Interface Diagnostic Mode
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
15-28
Flat Panel Registers
FR20
7 A B
FP Horizontal Panel Display Size LSB Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 20h shadowed only for pipeline A
FP Horizontal Panel Size LSB not shadowed for this pipeline
7-0
FP Horizontal Panel Size LSB This parameter signifies the end of FP Horizontal Display Enable and the start of FP Horizontal Blank time relative to the start of FP Horizontal Display Enable. The most significant bits are programmed in FR25 bits 3-0. In FP mode (FR01 bit 1 is set to 1), this parameter is counted using a counter which is clocked with FP dot clock divided by 8 in all modes and is independent of horizontal compensation. Programmed Value = Actual Value - 1
FR21
7 A B
FP Horizontal Sync Start LSB Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 21h shadowed only for pipeline A
FP Horizontal Sync Start LSB not shadowed for this pipeline
7-0
FP Horizontal Sync Start LSB In FP mode, this parameter is counted using a counter which is clocked with the FP dot clock divided by 8 in all modes and is independent of horizontal compensation. This parameter signifies the start of CRT HSync when not in CRT mode (when FR01 bit 0 is set to 0). The most significant bits are programmed in FR25 bits 7-4. Programmed Value = Actual Value - 1
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-29
FR22
7 A B
FP Horizontal Sync End Register
6 Reserved (R/W) xxx 5 4 3 2 FP Horizontal Sync End not shadowed for this pipeline 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 22h shadowed only for pipeline A
7-5 4-0
Reserved (R/W) FP Horizontal Sync End In FP mode, this parameter is counted using a counter which is clocked with the FP dot clock divided by 8 in all modes and is independent of horizontal compensation. This parameter signifies the end of CRT HSync when not in CRT mode (FR01 bit 0 is set to 0). Only the 5 least significant bits are programmed.
FR23
7 A B
FP Horizontal Total LSB Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 23h shadowed only for pipeline A
FP Horizontal Total LSB not shadowed for this pipeline
7-0
FP Horizontal Total LSB In FP mode, this parameter is counted using a counter which is clocked with the FP dot clock divided by 8 in all modes and is independent of horizontal compensation. This parameter signifies the end of FP Horizontal Blank time and the start of FP Horizontal Display Enable relative to the start of the previous FP Horizontal Display Enable, i.e., the total size from one Horizontal Enable to the next. The most significant bits are programmed in FR26 bits 3-0. Programmed Value = Actual Value - 5
efmp69030 Databook
Revision 1.3 11/24/99
15-30
Flat Panel Registers
FR24
7 A B
FP HSync (LP) Delay LSB Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 24h shadowed only for pipeline A
FP HSYNC (LP) Delay LSB not shadowed for this pipeline
7-0
FP HSync (LP) Delay LSB In FP mode, this parameter is counted using a counter which is clocked with the FP dot clock divided by 8 in all modes and is independent of horizontal compensation. This register is effective when FR27 bit 7 is set to 0 and signifies the start of FP HSync (LP) measured from start of FP Horizontal Display Enable. This allows FP HSync (LP) to be positioned independently from CRT HSync. The most significant bits are programmed in FR26 bits 7-4.
FR25
7 A B
FP Horizontal Overflow 1 Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 25h shadowed only for pipeline A
Reserved for Sync Start MSB Reserved for Panel Size MSB
not shadowed for this pipeline
7-4 3-0
Reserved (0) for FP Horizontal Sync Start MSB See description of FR20. Reserved (0) for FP Horizontal Panel Size MSB See description of FR21.
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-31
FR26
7 A B
FP Horizontal Overflow 2 Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 26h shadowed only for pipeline A
FP HSYNC (LP) Delay MSB not shadowed for this pipeline FP Horizontal Total MSB
7-4 3-0
FP HSync (LP) Delay MSB See description of FR23. FP Horizontal Total MSB See description of FR24.
FR27
7 A B Delay Disable
FP HSync (LP) Width and Disable Register
6 5 4 3 FP HSync LP Width not shadowed for this pipeline 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 27h shadowed only for pipeline A
7
FP HSync (LP) Delay Disable 0: FP HSync (LP) delay enable 1: FP HSync (LP) delay disable In FP mode, this parameter is counted using a counter which is clocked with the FP dot clock divided by 8 in all modes and is independent of horizontal compensation.
6-0
FP HSync (LP) Width Programmed Value = Actual Value - 1
efmp69030 Databook
Revision 1.3 11/24/99
15-32
Flat Panel Registers
FR30
7 A B
FP Vertical Panel Size LSB Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 30h shadowed only for pipeline A
FP Vertical Panel Size LSB not shadowed for this pipeline
In FP mode (FR01 bit 1 is set to 1), this register is used to establish the end of FP Vertical Display Enable and the start of FP Vertical Blank time. The most significant bits are programmed in FR35 bits 3-0. 7-0 FP Vertical Panel Size LSB Programmed Value = Actual Value - 1
FR31
7 A B
FP Vertical Sync Start LSB (FR31) Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 31h shadowed only for pipeline A
FP Vertical Sync Start LSB not shadowed for this pipeline
7-0
FP Vertical Sync Start LSB In FP mode (FR01 bit 1 is set to 1), this register signifies the start of CRT VSync (FR01 bit 0 is set to 0. The most significant bits are programmed in FR35 bits 7-4. Programmed Value = Actual Value - 1
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-33
FR32
7 A B
FP Vertical Sync End Register
6 Reserved (xxxx) not shadowed for this pipeline 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 32h shadowed only for pipeline A
FP Vertical Sync End
7-4
Reserved (R/W) In FP mode (FR01 bit 1 is set to 1), this register signifies the end of CRT VSync. Only the 4 least significant bits are programmed. FP Vertical Sync End Programmed Value = Actual Value - 1
3-0
FR33
7 A B
FP Vertical Total LSB Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 33h shadowed only for pipeline A
Vertical Total LSB not shadowed for this pipeline
7-0
Vertical Total LSB In FP mode (FR01 bit 1 is set to 1), this register is used to establish the end of FP Vertical Blank time and the start of FP Vertical Display Enable. The most significant bits are programmed in FR36 bits 3-0. FP Programmed Value = Actual Value - 2
efmp69030 Databook
Revision 1.3 11/24/99
15-34
Flat Panel Registers
FR34
7 A B
FP VSync (FLM) Delay LSB Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 34h shadowed only for pipeline A
FP VSync (FLM) Delay LSB not shadowed for this pipeline
7-0
FP VSync (FLM) Delay LSB In FP mode (FR01 bit 1 is set to 1), this register is effective when FR37 bit 7 is set to 0 and FR37 bit 6 is set to 0. This register signifies the start of FP VSync (FLM) measured from start of CRT VSync which is programmed in FR31. This allows FP VSync (FLM) to be located in a different position from CRT VSync. The most significant bits are programmed in FR36 bits 7-4. Programmed Value = Actual Value - 1
FR35
7 A B
FP Vertical Overflow 1 Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 35h shadowed only for pipeline A
Vertical Sync Start MSB not shadowed for this pipeline Vertical Panel Size MSB
7-4 3-0
FP Vertical Sync Start MSB See description of FR30. FP Vertical Panel Size MSB See description of FR31.
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-35
FR36
7 A V
FP Vertical Overflow 2 Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 36h shadowed only for pipeline A
FP FLM Delay MSB not shadowed for this pipeline FP Vertical Total MSB
7-4 3-0
FP FLM Delay Bits 11-8 See description of FR34. FP Vertical Total MSB See description of FR33.
FR37
7 A B
FP VSync (FLM) Disable Register
6 FLM Select 5 4 FP VSync (FLM) width not shadowed for this pipeline 3 2 1 Reserved (000) 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 37h shadowed only for pipeline A
FLM Delay
Note: When the FP Display engine is enabled (FR01 bit one is set to 1) it uses this register. 7 FP VSync (FLM) Delay Disable This bit is effective when FR37 bit 6 is set to 0. 0: FP VSync (FLM) delay enable 1: FP VSync (FLM) delay disable FP VSync (FLM) select 0: FP VSync (FLM) is generated using FR37 bit 7 and FP VSync (FLM) Delay (FR36 bits 6-4 and FR34) . 1: FP VSync (FLM) is the same as CRT VSync. FR37 bit 7 is ignored in this case. FP Vsync (FLM) width. These bits are effective only if bit 6 is 0. Programmed value = actual value -1 2-0 Reserved These bits should always be written to with a value of zero.
6
5-3
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Revision 1.3 11/24/99
15-36
Flat Panel Registers
FR40
7 A B
Horizontal Compensation Register
6 Reserved (00) 5 EGHC (0) 4 THCP (0:0) not shadowed for this pipeline 3 2 ETHC (0) 1 EHC (0) 0 EHCP (0)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 40h shadowed only for pipeline A
Note: This register is used in FP mode (FR01 Bit 1 set to 1) 7-6 5 Reserved (R/W) FP Enable Graphics Horizontal Compensation (EGHC) 0: Disable graphics mode horizontal compensation. 1: Enable graphics mode horizontal compensation which consists of horizontal stretching and FR41 is used to specify stretching for different horizontal resolutions. This bit is effective only when bit 0 is 1. Text Horizontal Compensation Priority (THCP)
Bits 43
4-3
Text Horizontal Compensation Priority (THCP) Allow 9-dot compression to 8-dot if needed. If horizontal panel size is wide enough, 8-dot text remains 8-dot text and 9-dot text remains 9-dot text. If horizontal panel size is not wide enough, then 8-dot text remains 8-dot text and 9-dot text is forced to 8-dot text. This is the default after reset. No compression or expansion. 8-dot text remains 8-dot text and 9-dot text remains as 9-dot text regardless of horizontal panel size. Allow 8-dot expansion to 9-dot, or 9-dot compression to 8-dot, depending on horizontal panel size. If horizontal panel size is wide enough, 8-dot text is forced to 9-dot text and 9-dot text remains 9-dot text. If horizontal panel size is not wide enough then 8-dot text remains 8-dot text and 9-dot text is forced to 8dot text. Allow 8-dot and 9-dot expansion to 10-dot, or 8-dot expansion to 9-dot, or 9-dot compression to 8-dot, depending on horizontal panel size. If horizontal panel size is wide enough, 8-dot text is forced to 10-dot text and 9-dot text is forced to 10dot text. Otherwise, if horizontal panel size is wide enough, 8-dot text is forced to 9-dot text and 9-dot text remains 9-dot text. If horizontal panel size is not wide enough, then 8-dot text remains 8-dot text and 9-dot text is forced to 8-dot text.
00
01
10
11
These bits are effective only when bit 0 is 1 and bit 2 is 1. These bits determine the text mode compression/stretching method to be applied if horizontal panel size is wide enough. If after applying the specified text compression/stretching, the horizontal panel size is still wider than the stretched image then further stretching will be applied using the same algorithm used for horizontal graphics compensation.
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers 2 Enable Text Horizontal Compensation (ETHC) 0: Disable text mode horizontal compensation. This is the default after reset. 1: Enable text mode horizontal compensation.
15-37
This bit is effective only when bit 0 is 1. Text mode horizontal compensation priority/method is specified in bits 4-3. 1 Enable Horizontal Centering (EHC) 0: Disable horizontal centering. This is the default after reset. 1: Enable horizontal centering. Horizontal left and right borders will be computed automatically. Enable Horizontal Compensation (EHCP) 0: Disable horizontal compensation. This is the default after reset. 1: Enable horizontal compensation.
0
efmp69030 Databook
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15-38
Flat Panel Registers
FR41
7 A
Horizontal Stretching Register
6 Reserved (0000) 5 4 3 Reserved (R/W) (0) not shadowed for this pipeline 2 Hor Stretch 1024 Col 1 Hor Stretch 800 Col 0 Hor Stretch 640 Col
read/write at I/O address 3D1h with index at I/O address 3D0h set to 41h shadowed only for pipeline A
B
Note: This register is used when FR01 bit 1 is set to 1 and FR40 bit 0 is set to 1 and graphics mode is enabled. This register must be set before FR40. 7-4 3 2 Reserved Reserved (R/W) (reset state: 0) FP Enable Horizontal Stretching for 1024-column Graphics Mode 0: Disable horizontal stretching for 1024-column graphics mode. 1: Enable horizontal stretching for 1024-column graphics mode. Note: That 1024-column graphics mode includes 512-column graphics mode with horizontal pixel doubling enabled. 1 FP Enable Horizontal Stretching for 800-column Graphics Mode 0: Disable horizontal stretching for 800-column graphics mode. 1: Enable horizontal stretching for 800-column graphics mode. Note: That 800-column graphics mode includes 400-column graphics mode with horizontal pixel doubling enabled. 0 FP Enable Horizontal Stretching for 640-column Graphics Mode 0: Disable horizontal stretching for 640-column graphics mode. 1: Enable horizontal stretching for 640-column graphics mode. Note: The 640-column graphics mode includes 320-column graphics mode with horizontal pixel doubling enabled.
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-39
FR48
7 A
Vertical Compensation Register
6 Reserved (R/W) (000) 5 4 ETVS (0) 3 Text Mode Stretch (0) 2 EVLR (0) 1 Vertical Centering (0) 0 EVCP (0)
read/write at I/O address 3D1h with index at I/O address 3D0h set to 48h shadowed only for pipeline A
B
not shadowed for this pipeline
Note: When the FP Display engine is enabled (when FR01 bit 1 is set to 1), it uses this register. 7-5 4 Reserved (R/W) (reset state: 0) Enable Text Mode Vertical Stretching (ETVS) 0: Disable vertical stretching (default) 1: Enable vertical stretching Text Mode Vertical Stretching Priority 0: Priority: ETVS, EVLR (default) 1: Priority: EVLR, ETVS This bit is effective in text modes if bits 2 and 4 are set. Enable Vertical Line Replication (EVLR) 0: Disables vertical line replication (default) 1: Enables vertical line replication This bit is effective in both text and graphics modes. Enable Vertical Centering 0: Disables vertical centering (default) 1: Enables vertical centering This bit is effective only when bit 0 is "1". Enable Vertical Compensation (EVCP) 0: Disables vertical compensation feature (default) 1: Enables vertical compensation feature
3
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
15-40
Flat Panel Registers
FR49-4C
7 A B
Text Mode Vertical Stretching Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 49h-4Ch shadowed only for pipeline A
Replication Specification not shadowed for this pipeline
7-0
Replication Specifications
Bits 70 00 01 10 11
Replication Specifications No replication Replicate once Replicate twice Replicate three times
Font lines beyond 16 are not replicated. This register specifies the new text mode vertical stretching (along with FR4A, FR4B, FR4C). FR49(MSB), FR4A(LSB) and FR4B (MSB), FR4C(LSB) constitute two 16 bit registers. Each of the 16 pairs of bits specify scan line replication as shown above. FR49: FR4A: FR4B: FR4C: Text Mode Vertical Stretching 0 MSB Text Mode Vertical Stretching 0 LSB Text Mode Vertical Stretching 1 MSB Text Mode Vertical Stretching 1 LSB
FR4D
7 A B
Vertical Line Replication Register
6 VLRHH not shadowed for this pipeline 5 4 3 2 VLRHL 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 4Dh
This register is used in FP mode (FR01 bit 1 set to 1) and when vertical line replication is enabled. The 4 bit number specifies the number of lines between replicated lines. Double scanned lines are counted. The state machine starts stretching by using the lower nibble value. If the stretched display does not fit it uses the next higher value. The process continues until the count is equal to upper nibble value or the display fits. The lower nibble value must be less than or equal to upper nibble value. Set this register before FR40. 7-4 3-0 FP Vertical Line Replication Height High (VLRHH) FP Vertical Line Replication Height Low (VLRHL)
efmp69030 Databook
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Flat Panel Registers
15-41
FR4E
7 A B
Selective Vertical Stretching Disable Register
6 Reserved (xx) 5 Disable 600 Graph 4 Disable 480 Graph 3 Disable 400 Graph 2 Disable 350 Graph 1 Disable 400 Text 0 Disable 350 Text
read/write at I/O address 3D1h with index at I/O address 3D0h set to 4Eh shadowed only for pipeline A
not shadowed for this pipeline
This register is used to selectively disable vertical stretching based on the vertical display end parameter. The register is qualified by master enable bits in FR48. Set this register before setting FR40. 7-6 5 Reserved (R/W) Disable 600-line Graphics Stretching 0: Disables stretching 1: Enables stretching Disable 480-line Graphics Stretching 0: Disables stretching 1: Enables stretching Disable 400-line Graphics Stretching 0: Disables stretching 1: Enables stretching Disable 350-line Graphics Stretching 0: Disables stretching 1: Enables stretching Disable 400-line Text Stretching 0: Disables stretching 1: Enables stretching Disable 350-line Text Stretching 0: Disables stretching 1: Enables stretching
4
3
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
15-42
Flat Panel Registers
FR70
7 A B
TMED Red Seed Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 70h shadowed only for pipeline A
TMED Red Seed not shadowed for this pipeline
7-0
TMED Red Seed The 8-bit value written to this register specifies the seed value used in the TMED algorithm for red pixel data to improve images on dual-scan passive matrix LCD panels.
FR71
7 A B
TMED Green Seed Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 71h shadowed only for pipeline A
TMED Green Seed not shadowed for this pipeline
7-0
TMED Green Seed The 8-bit value written to this register specifies the seed value used in the TMED algorithm for green pixel data to improve images on dual-scan passive matrix LCD panels.
FR72
7 A B
TMED Blue Seed Register
6 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to72h shadowed only for pipeline A
TMED Blue Seed not shadowed for this pipeline
7-0
TMED Blue Seed The 8-bit value written to this register specifies the seed value used in the TMED algorithm for blue pixel data to improve images on dual-scan passive matrix LCD panels.
efmp69030 Databook
Revision 1.3 11/24/99
Flat Panel Registers
15-43
FR73
7 A B TMED Enable
TMED Control Register
6 Scheme Select 5 4 3 2 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 73h shadowed only for pipeline A
Shades per Color Select Horizontal Beat Suppression
not shadowed for this pipeline
Note: The recommended default value to which this register should be set is F5h. 7 TMED Enable 0: Disables TMED. 1: Enables TMED. TMED Scheme Select 0: Selects TMED energy distribution scheme 2. 1: Selects TMED energy distribution scheme 1. TMED Shades per Color Select 00: Selects 33 shades for red, 65 shades for green, and 33 shades for blue. 01: Selects 65 shades for red, green, and blue. 10: Selects 129 shades for red, green, and blue. 11: Selects 256 shades for red, green, and blue. TMED Horizontal Beat Suppression The value written to these 4 bits specifies the horizontal beat suppression factor.
6
5-4
3-0
efmp69030 Databook
Revision 1.3 11/24/99
15-44
Flat Panel Registers
FR74
7 A B
TMED2 Control Register
6 5 4 3 Method 1 Enable not shadowed for this pipeline 2 Method 2 Enable 1 0
read/write at I/O address 3D1h with index at I/O address 3D0h set to 74h shadowed only for pipeline A
Vertical Beat Suppression Method 1 Method 2 Scheme Sel Scheme Sel
Note: The recommended default value to which this register should be set is 5Fh. 7-4 3 Vertical Beat Suppression The value written to these 4 bits specifies the vertical beat suppression factor. TMED2 Method 1 Enable 0: Disables TMED2 method 1. 1: Enables TMED2 method 1. TMED2 Method 2 Enable 0: Disables TMED2 method 2. 1: Enables TMED2 method 2. TMED2 Method 1 Scheme Select 0: Selects scheme 1. 1: Selects scheme 2. TMED2 Method 2 Scheme Select 0: Selects scheme 1. 1: Selects scheme 2.
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-1
Chapter 16 Multimedia Registers
Introduction
Chapter 16 describes the Multimedia Registers for the 69030 Dual HiQVideo Accelerator. Table 16-1: Multimedia Registers
Name MR00 MR01 MR02 MR03 MR04 MR05 MR06-08 MR09-0B MR0C MR0E MR0F MR10 MR11 MR12 MR13 MR14 MR15 MR16 MR17 MR18 MR1E/9E MR1F/9F MR20/A0 MR21/A1 MR22/A2-24/A4 MR25/A5-27/A7 MR28/A8 MR2A/AA MR2B/AB MR2C/AC MR2D/AD MR2E/AE MR2F/AF MR30/B0 MR31/B1 MR32/B2 MR33/B3 MR34/B4 MR3C/BC MR3D/BD-3F/BF MR40/C0-42/C2 MR43/C3 MR44/C4 Register Function Module Capability Register Secondary Capability Register Capture Control 1 Register Capture Control 2 Register Capture Control 3 Register Capture Control 4 Register Capture Memory Address PTR1 Registers Capture Memory Address PTR2 Registers Capture Memory Width (Span) Register Capture Window X-LEFT Low Register Capture Window X-LEFT High Register Capture Window X-RIGHT Low Register Capture Window X-RIGHT High Register Capture Window Y-TOP Low Register Capture Window Y-TOP High Register Capture Window Y-BOTTOM Low Register Capture Window Y-BOTTOM High Register H-SCALE Register V-SCALE Register Capture Frame/Field Drop Count Register Playback Control 1 Register Playback Control 2 Register Playback Control 3 Register Double Buffer Status & Control Register Playback Memory Address PTR1 Registers Playback Memory Address PTR2 Registers Playback Memory Line Fetch Width Register Playback Window X-LEFT Low Register Playback Window X-LEFT High Register Playback Window X-RIGHT Low Register Playback Window X-RIGHT High Register Playback Window Y-TOP Low Register Playback Window Y-TOP High Register Playback Window Y-BOTTOM Low Register Playback Window Y-BOTTOM High Register H-ZOOM Register V-ZOOM Register Memory Line Out Total Register Color Key Control Register Color Keys Registers Color Key Masks Registers Display Scanline Count Low Register (shadowed) Display Line Count Low Register (shadow) Access Via 3D3h read-only read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read-only read-only Index at 3D2h Set to Value 00h 01h 02h 03h 04h 05h 06h-08h 09h-0Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 1Eh/9Eh 1Fh/9Fh 20h/A0h 21h/A1h 22h/A2h-24h/A4h 25h/A5h-27h/A7h 28h/A8h 2Ah/AAh 2Bh/ABh 2Ch/ACh 2Dh/ADh 2Eh/AEh 2Fh/AFh 30h/B0h 31h/B1h 32h/B2h 33h/B3h 34h/B4h 3Ch/BCh 3Dh/BDh-3Fh/BFh 40h/C0h-42h/C2h 43h/C3h 44h/C4h
efmp69030 Databook
Revision 1.3 11/24/99
16-2
Multimedia Registers
MR00
7 A & B
Module Capability Register
6 5 Reserved 4 3 2 1 Capture 0 Playback
read-only at I/O address 3D3h with index at address 3D2h set to 00h shared by both pipelines A and B
7-2 1
Reserved Capture Available 0: Absent 1: Included Playback Available 0: Absent 1: Included
0
MR01
7 A & B
Secondary Capability Register
6 5 4 Reserved 3 2 1 0
read-only at I/O address 3D3h with index at address 3D2h set to 01h shared by both pipelines A and B
7-0
Reserved
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-3
MR02
7 A & B Field Det Method (0)
Capture Control 1 Register
6 Field Det Polarity (0) 5 VSYNC Polarity (0) 4 HSYNC Polarity (0) 3 RGB Mode (0) 2 Color (0) 1 Reserved (0) 0 Interlace (0)
read/write at I/O address 3D3h with index at address 3D2h set to 02h shared by both pipelines A and B
7
Field Detect Method 0: Trailing Edge of V 1: Leading Edge of V Field Detect Polarity 0: Normal 1: Inverted VSYNC Polarity 0: Low asserted 1: High asserted HSYNC Polarity 0: Low asserted 1: High asserted RGB Mode 0: RGB16 1: RGB15 Color 0: YUV 1: RGB
6
5
4
3
2
1 0
Reserved Interlace 0: Interlace Enabled 1: Non-Interlace
efmp69030 Databook
Revision 1.3 11/24/99
16-4
Multimedia Registers
MR03
7 A & B
Capture Control 2 Register
6 5 Y-Scale (0) 4 X-Scale (0) 3 2 1 0 Capture Enable (0)
read/write at I/O address 3D3h with index at address 3D2h set to 03h shared by both pipelines A and B
V Scaling Method (00) Field Select Frame/Field Continuous/ Capture Single (0) (0) (0)
7-6
V Scaling Method 00: Normal 01: Reserved 10: Overwrite 11: Reserved Y-Scale Enable 0: Disabled 1: Scaled on V X-Scale Enable 0: Disabled 1: Scaled on H Field Select 0: Field 0 1: Field 1 Bit 3 is only effective when bit 2 is set to 1. Frame/Field Capture 0: Frame 1: Field Continuous/Single Frame/Field Video Data Capture 0: Causes the continuous capturing of video data from the video data port. 1: Causes the capture of a single frame or field (depending on the setting of bit 2 of this register) from the video data port. Capture Enable 0: Stop 1: Start
5
4
3
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-5
MR04
7 A & B
Capture Control 3 Register
6 Shift Fields Down (0) 5 Dbl Buffer Ptr Select (0) 4 Dbl Buffer Enable (0) 3 Dbl Buffer Mode Select (0) 2 Horiz Filter Enable (0) 1 Y-Capture Direction (0) 0 X-Capture Direction (0)
read/write at I/O address 3D3h with index at address 3D2h set to 04h shared by both pipelines A and B
Cap Frm/Fld Drop Enable (0)
7
Capture Frame/Field Drop Enable 0: Causes the capture of video data from the video data port without dropping frames or fields. 1: Causes the dropping of the number of frames/fields specified in the Capture Frame/Field Drop Count Register (MR18) between every frame/field that is saved. Shift Fields Down 0: Keeps the video playback window at its normal location -- i.e., it is not shifted vertically. 1: Shifts the odd fields in the video playback window down by one scanline. Double Buffer Pointer Select 0: PTR1 in use 1: PTR2 in use Double Buffer Enable 0: Double buffering disabled 1: Double buffering enabled Double Buffer Mode Select 0: CPU Forced 1: V Locked Horizontal Filter Enable 0: No Filter 1: Filter pixels with horizontal filter Y-Capture Direction 0: Normal: top to bottom 1: Flipped: bottom to top X-Capture Direction 0: Normal: left to right 1: Mirrored: right to left Note: Changing the X- or Y- capture direction (Bits 1-0) will also require a change in the acquisition memory address pointer.
6
5
4
3
2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
16-6
Multimedia Registers
MR05
7 A & B
Capture Control 4 Register
6 UV SWAP (0) 5 Pixel Qual Polarity (0) 4 Pixel Qual Enable (0) 3 Input VSYNC (0) 2 Last Frame Captured (0) 1 Current Address (0) 0 Actual Capture (0)
read/write at I/O address 3D3h with index at address 3D2h set to 05h shared by both pipelines A and B
Input Byte Swap (0)
7
Input Byte Swap 0: Y on low 8 input pins, UV on high 8 input pins 1: Y on high 8 input pins, UV on low 8 input pins (VESA style) UV SWAP 0: Normal UV sequence 1: Exchange U and V Pixel Qualifier Polarity 0: Non-inverted 1: Inverted Pixel Qualifier Enable 0: Continuous pixels gated by blank 1: PIXEN qualifies valid pixels Input VSYNC (read only) (After polarity correction) Last Frame Captured (read only) 0: PTR1 1: PTR2 (Effective only with double buffering) Current Address Pointer (read only) 0: PTR1 (Acquisition memory pointer 1) 1: PTR2 (Acquisition memory pointer 2) Indicates which buffer is being captured if double buffering is enabled. Actual Capture (read only) 0: Hardware frame capture stopped 1: Hardware frame capture active (synchronized to V)
6
5
4
3 2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-7
MR06
7 A & B
Capture Memory Address PTR1 Low Register
6 5 4 3 2 1 Reserved Capture Memory Address PTR1 Low Bits 7-3 (000) 0
read/write at I/O address 3D3h with index at address 3D2h set to 06h shared by both pipelines A and B
7-3 2-0
Capture Memory Address PTR1 Low Bits 7-3 Reserved
MR07
7 A & B
Capture Memory Address PTR1 Mid Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 07h shared by both pipelines A and B
Capture Memory Address PTR1 Mid Bits 15-8
7-0
Capture Memory Address PTR1 Mid Bits 15-8
MR08
7 A & B
Capture Memory Address PTR1 High Register
6 Reserved Capture Memory Address PTR1 High Bits 21-16 (00) 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 08h shared by both pipelines A and B
7-6 5-0
Reserved Capture Memory Address PTR1 High Bits 21-16
efmp69030 Databook
Revision 1.3 11/24/99
16-8
Multimedia Registers
MR09
7 A & B
Capture Memory Address PTR2 Low Register
6 5 4 3 2 1 Reserved Capture Memory Address PTR2 Low Bits 7-3 (000) 0
read/write at I/O address 3D3h with index at address 3D2h set to 09h shared by both pipelines A and B
7-3 2-0
Capture Memory Address PTR2 Low Bits 7-3 Reserved
MR0A
7 A & B
Capture Memory Address PTR2 Mid Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 0Ah shared by both pipelines A and B
Capture Memory Address PTR2 Mid Bits 15-8
7-0
Capture Memory Address PTR2 Mid Bits 15-8
MR0B
7 A & B
Capture Memory Address PTR2 High Register
6 Reserved Capture Memory Address PTR2 High Bits 21-16 (00) 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 0Bh shared by both pipelines A and B
7-6 5-0
Reserved Capture Memory Address PTR2 High Bits 21-16
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-9
MR0C
7 A & B
Capture Line Memory Storage Width Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 0Ch shared by both pipelines A and B
Memory Width (span) Bits 7-0
7-0
Memory Width (Span) Bits 7-0 This value is calculated as follows: ( (width of line in pixels) / (number of pixels per quadwords) ) - 1.
MR0E
7 A & B
Capture Window X-LEFT Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 0Eh shared by both pipelines A and B
Capture Window X-LEFT Bits 7-0
7-0
Acquisition Window X-LEFT Bits 7-0
MR0F
7 A & B
Capture Window X-LEFT High Register
6 5 Reserved 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 0Fh shared by both pipelines A and B
Capture Window X-LEFT Bits 10-8
7-3 2-0
Reserved Capture Window X-LEFT Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
16-10
Multimedia Registers
MR10
7 A & B
Capture Window X-RIGHT Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 10h shared by both pipelines A and B
Capture Window X-RIGHT Bits 7-0
7-0
Acquisition Window X-RIGHT Bits 7-0
MR11
7 A & B
Capture Window X-RIGHT High Register
6 5 Reserved 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 11h shared by both pipelines A and B
Capture Window X-RIGHT Bits 10-8
7-3 2-0
Reserved Capture Window X-RIGHT Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-11
MR12
7 A & B
Capture Window Y-TOP Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 12h shared by both pipelines A and B
Capture Window Y-TOP Bits 7-0
7-0
Acquisition Window Y-TOP Bits 7-0
MR13
7 A & B
Capture Window Y-TOP High Register
6 5 Reserved 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 13h shared by both pipelines A and B
Capture Window Y-TOP Bits 10-8
7-3 2-0
Reserved Capture Window Y-TOP Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
16-12
Multimedia Registers
MR14
7 A & B
Capture Window Y-BOTTOM Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 14h shared by both pipelines A and B
Capture Window Y-BOTTOM Bits 7-0
7-0
Acquisition Window Y-BOTTOM Bits 7-0
MR15
7 A & B
Capture Window Y-BOTTOM High Register
6 5 Reserved 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 15h shared by both pipelines A and B
Capture Window Y-BOTTOM Bits 10-8
7-3 2-0
Reserved Capture Window Y-BOTTOM Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-13
MR16
7 A & B
H-SCALE Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 16h shared by both pipelines A and B
H-SCALE Bits 7-0
7-0
H-SCALE Bits 7-0
MR17
7 A & B
V-SCALE Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 17h shared by both pipelines A and B
V-SCALE Bits 7-0
7-0
V-SCALE Bits 7-0
MR18
7 A & B
Capture Frame/Field Drop Count Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at !/O address 3Dh2 set to 18h shared by both pipelines A and B
Capture Frame/Field Drop Count 7-0
7-0
Capture Frame/Field Drop Count When the dropping of frames/fields is enabled by setting bit 2 of the Capture Control 2 Register (MR03) to 1, these 8 bits set the number of captured frames/fields to be dropped between every frame/field that is captured and saved.
efmp69030 Databook
Revision 1.3 11/24/99
16-14
Multimedia Registers
MR1E/9E
7 PB 1 PB 2 Playback Engine En (1) Playback Engine En (1)
Playback Control 1 Register
6 Playback Assign (0) Playback Assign (0) 5 4 Playback Interlacing (0) Playback Interlacing (0) 3 Playback V-Zoom (0) Playback V-Zoom (0) 2 Playback H-Zoom (0) Playback H-Zoom (0) 1 Playback Y-Display (0) Playback Y-Display (0) 0 Playback H-Display (0) Playback H-Display (0)
read/write at I/O address 3D3h with index at address 3D2h set to index 1Eh/9Eh shared & shadowed for each playback engine at MR1E, and cross-shared for the other at MR9E
Playback Layering (0)
7
Playback Engine Enable 0: The video playback engine to which this register belongs is disabled. This means that all clocks to this playback engine have been shut off, and this playback engine can be reassigned from one pipe to another using bit 6 of this register. 1: The video playback engine to which this register belongs is enabled. This means that all clocks to this playback engine are connected, and this playback engine should not be reassigned from one pipe to another. This is the default after reset. Playback Engine Pipeline Assignment For playback engine 1's copy of this register: 0: Video playback engine 1 is assigned to pipeline A. 1: Video playback engine 1 is assigned to pipeline B. For playback engine 2's copy of this register: 0: Video playback engine 2 is assigned to pipeline B. 1: Video playback engine 2 is assigned to pipeline A. Playback Window Layering This bit has effect only when both playback engines are being used on the same pipeline. If both playback engines are being used on pipeline A: This bit is accessible via MR1E in pipeline A's copy of the MR register set and via MR9E in pipeline B's copy of the MR register set. 0: If the playback windows for the two playback engines ever overlap, the video playback window for video playback engine 1 will be on top. 1: If the playback windows for the two playback engines ever overlap, the video playback window for video playback engine 2 will be on top. If both playback engines are being used on pipeline B: This bit is accessible via MR1E in pipeline B's copy of the MR register set and via MR9E in pipeline A's copy of the MR register set. 0: If the playback windows for the two playback engines ever overlap, the video playback window for video playback engine 2 will be on top. 1: If the playback windows for the two playback engines ever overlap, the video playback window for video playback engine 1 will be on top.
6
5
4
Playback Interlacing 0: Selects non-interlaced playback. 1: Selects interlaced playback. Playback Vertical Zoom Control 0: Vertical zoom controlled normally. 1: Vertical zoom controlled via V-Zoom Register. Revision 1.3 11/24/99
3
efmp69030 Databook
Multimedia Registers
16-15
2
Playback Horizontal Zoom Control 0: Vertical zoom controlled normally. 1: Vertical zoom controlled via H-Zoom Register. Playback Y-Display Direction 0: Normal -- top-to-bottom. 1: Flipped vertically -- bottom-to-top. Playback X-Display Direction 0: Normal -- left-to-right. 1: Flipped vertically -- right-to-left.
1
0
efmp69030 Databook
Revision 1.3 11/24/99
16-16
Multimedia Registers
MR1F/9F
7 PB 1 PB 2 V Inter Enable (0) V Inter Enable (0)
Playback Control 2 Register
6 V Inter Mode (0) V Inter Mode (0) 5 H Inter Enable (0) H Inter Enable (0) 4 Reserved (0) Reserved (0) 3 Color Mode Select (0) Color Mode Select (0) 2 Reserved (0) Reserved (0) 1 UV Sign (0) UV Sign (0) 0 Color Type Select (0) Color Type Select (0)
read/write at I/O address 3D3h with index at address 3D2h set to 1Fh/9Fh shared & shadowed for each playback engine at MR1F, and cross-shared for the other at MR9F
7
V Interpolate Enable 0: Disable 1: Enable V Interpolate Mode 0: De-block 1: Running Average (when bit 7 is set) H Interpolate Enable Reserved Color Mode Select 0: YUV 1: RGB See color mode table below. Reserved UV Sign 0: UV Unsigned (signed offset) 1: UV Signed (2's complement) Color Type Select (See bit 3) 0: Normal (U and V, or RGB16) 1: Exchange U and V positions, or RGB15 Color Mode Table for bit-3:
Bit 3210 0x00 0x01 0x10 0x11 1xx0 1xx1 Color Format YUV 4:2:2 YVU 4:2:2; UV Swap YUV 4:2:2; UV=2's comp YVU 4:2:2; UV=2'comp, UV swap RGB16; R5G6B5 (B=LSB) RGB15, xR5G5B5 (B=LSB)
6
5 4 3
2 1
0
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-17
MR20/A0
7 Playback PB Vert. Autoctr 1 Enable Playback PB Vert. Autoctr 2 Enable
Playback Control 3 Register
6 Playback Width Source Playback Width Source 5 Playback Pointer Select Playback Pointer Select 4 CPU Double Buffer Flag CPU Double Buffer Flag 3 Playback Pointer Select 2 Playback Pointer Select 2 2 Double Buffer Trigger Double Buffer Trigger 1 Reserved 0
read/write at I/O address 3D3h with index at address 3D2h set to 20h/A0h shared & shadowed for each playback engine at MR20, and cross-shared for the other at MRA0
Reserved
7
Playback Vertical Auto-Centering Enable 0: Allow software to employ a delay to properly center the playback window vertically. This is done usually via bit 4 of the Pixel Pipeline Configuration Register 1 (XR81). 1: Activate a hardware-based auto-centering mechanism. Playback Width Source 0: Uses MR28 for Playback width 1: Uses MR34 for Playback width Playback Pointer Select 1 0: The pointer to the location in the frame buffer from which frames/fields of video data are played back is selected by bit 4 of this register. 1: The pointer to the location in the frame buffer from which frames/fields of video data are played back is controlled by bit 3 of this register. CPU Double Buffer Flag 0: Playback memory address PTR1 1: Playback memory address PTR2 Playback Pointer Select 2 0: The pointer to the location in the frame buffer from which frames/fields of video data are played back is selected by bit 4 of this register. 1: The pointer to the location in the frame buffer from which frames/fields of video data are played back toggles between the addresses indicated by PTR1 and PTR2 after each frame/ field captured.
Bit 43 0 1 0 0 1 1 X X 0 1 0 1 Playback Pointer Select Selects playback memory pointer address 1 Selects playback memory pointer address 2 Selects playback memory pointer address 1 Pointer to the location from which frames/fields of data are read toggles between addresses indicated by PTR1and PTR2 after each frame/field captured Selects playback memory pointer address 2 Pointer to the location from which frames/fields of data are read toggles between addresses indicated by PTR1and PTR2 after each frame/field captured
6
5
4
3
5 0 0 1 1 1 1
2
Double Buffer Trigger 0: Retains old PTR. 1: Takes new PTR on next VSYNC if bit 5 is set to 1. Reserved
1-0
efmp69030 Databook
Revision 1.3 11/24/99
16-18
Multimedia Registers
MR21/A1
7 PB 1
Double Buffer Status Register
6 5
Reserved
read/write at I/O address 3D3h with 3D2h set to index 21h/A1h shadowed for each playback engine at MR21, and cross-shared for the other at MRA1
4 3 2 1
Playback 1 Data Buffer Ptr in Use (x) Playback 2 Data Buffer Ptr in Use (x)
0
Playback 1 Data Buffer Trig Status (x) Playback 2 Data Buffer Trig Status (x)
(0000:00) Reserved
PB 2
(0000:00)
7-2
Reserved These bits always return the value of 0 when read.
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers 1
16-19
Video Data Double Buffer Pointer In Use Note: This is a read-only bit. Any value written to this bit will be ignored. 0: The playback engine to which this shadow of this register belongs is currently drawing video data from the frame buffer location pointed to via its shadow of pointer #1 (i.e., the offset pointed to by MR22-MR24 / MRA2-MRA4). 1: The playback engine to which this shadow of this register belongs is currently drawing video data from the frame buffer location pointed to via its shadow of pointer #2 (i.e., the offset pointed to by MR25-MR27 / MRA5-MRA7). Video Data Double Buffer Trigger Status Note: This is a read-only bit. Any value written to this bit will be ignored. 0: Taken 1: Pending
0
efmp69030 Databook
Revision 1.3 11/24/99
16-20
Multimedia Registers
MR22/A2
7 PB 1 PB 2
Playback Memory Address PTR1 Low Register
6 5 4 3 2 1 Reserved (000) Reserved (000) 0
read/write at I/O address 3D3h with index at address 3D2h set to 22h/A2h shadowed for each playback engine at MR22, and cross-shared for the other at MRA2
Playback Engine 1 Memory Address PTR1 Low Bits 7-3 Playback Engine 2 Memory Address PTR1 Low Bits 7-3
7-3 2-0
Playback Memory Address PTR1 Low Bits 7-3 Reserved
MR23/A3
7 PB 1 PB 2
Playback Memory Address PTR1 Mid Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 23h/A3h shadowed for each playback engine at MR23, and cross-shared for the other at MRA3
Playback Engine 1 Memory Address PTR1 Mid Bits 15-8 Playback Engine 2 Memory Address PTR1 Mid Bits 15-8
7-0
Playback Memory Address PTR1 Mid Bits 15-8
MR24/A4
7 PB 1 PB 2
Playback Memory Address PTR1 High Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 24h/A4h shadowed for each playback engine at MR24, and cross-shared for the other at MRA4
Reserved (00) Reserved (00) Playback Engine 1 Memory Address PTR1 High Bits 21-16 Playback Engine 2 Memory Address PTR1 High Bits 21-16
7-6 5-0
Reserved Playback Memory Address PTR1 High Bits 21-16
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-21
MR25/A5
7 PB 1 PB 2
Playback Memory Address PTR2 Low Register
6 5 4 3 2 1 Reserved (000) Reserved (000) 0
read/write at I/O address 3D3h with index at address 3D2h set to 25h/A5h shadowed for each playback engine at MR25, and cross-shared for the other at MRA5
Playback Engine 1 Memory Address PTR2 Low Bits 7-3 Playback Engine 2 Memory Address PTR2 Low Bits 7-3
7-3 2-0
Playback Memory Address PTR2 Low Bits 7-3 Reserved
MR26/A6
7 PB 1 PB 2
Playback Memory Address PTR2 Mid Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 26h/A6h shadowed for each playback engine at MR26, and cross-shared for the other at MRA6
Playback Engine 1 Memory Address PTR2 Mid Bits 15-8 Playback Engine 2 Memory Address PTR2 Mid Bits 15-8
7-0
Playback Memory Address PTR2 Mid Bits 15-8
MR27/A7
7 PB 1 PB 2
Playback Memory Address PTR2 High Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 27h/A7h shadowed for each playback engine at MR27, and cross-shared for the other at MRA7
Reserved (00) Reserved (00) Playback Engine 1 Memory Address PTR2 High Bits 21-16 Playback Engine 2 Memory Address PTR2 High Bits 21-16
7-6 5-0
Reserved Playback Memory Address PTR2 High Bits 21-16
efmp69030 Databook
Revision 1.3 11/24/99
16-22
Multimedia Registers
MR28/A8
7 PB 1 PB 2
Playback Line Memory Fetch Width Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 28h/A8h shadowed for each playback engine at MR28, and cross-shared for the other at MRA8
Playback Engine 1 Line Memory Fetch Width Bits 7-0 Playback Engine 1 Line Memory Fetch Width Bits 7-0
7-0
Playback Line Memory Fetch Width Bits 7-0 These 8 bits specify the number of quadwords read by the playback engine from the frame buffer to display a horizontal line's worth of video data. Normally, this value is set equal to the actual number of quadwords required to store a horizontal line's worth of video data captured from the video data port -- i.e., normally this value is the same as that of register MR0C. If bit 6 of the Playback Control 3 Register (MR0C) is set to 0 then this register also specifies the number of quadwords out of a horizontal line's worth of video data that is actually played back, starting at the left-most edge of the video playback window. This value is calculated as follows: ( (width of line in pixels) / (number of pixels per quadwords) ) - 1.
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-23
MR2A/AA
7 PB 1 PB 2
Playback Window X-LEFT Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 2Ah/AAh shadowed for each playback engine at MR2A, and cross-shared for the other at MRAA
Playback Window 1 X-LEFT Bits 7-0 (0000:0000) Playback Window 2 X-LEFT Bits 7-0 (0000:0000)
7-0
Playback Window X-LEFT Bits 7-0
MR2B/AB
7 PB 1 PB 2
Playback Window X-LEFT High Register
6 5 Reserved (0000:0) Reserved (0000:0) 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 2Bh/ABh shadowed for each playback engine at MR2B, and cross-shared for the other at MRAB
Playback Window 1 X-LEFT Bits 10-8 (000) Playback Window 2 X-LEFT Bits 10-8 (000)
7-3 2-0
Reserved Playback Window X-LEFT Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
16-24
Multimedia Registers
MR2C/AC
7 PB 1 PB 2
Playback Window X-RIGHT Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 2Ch/ACh shadowed for each playback engine at MR2C, and cross-shared for the other at MRAC
Playback Window 1 X-RIGHT Bits 7-0 (0000:0000) Playback Window 2 X-RIGHT Bits 7-0 (0000:0000)
7-0
Playback Window X-RIGHT Bits 7-0
MR2D/AD
7 PB 1 PB 2
Playback Window X-RIGHT High Register
6 5 Reserved (0000:0) Reserved (0000:0) 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 2Dh/ADh shadowed for each playback engine at MR2D, and cross-shared for the other at MRAD
Playback Window 1 X-RIGHT Bits 10-8 (000) Playback Window 2 X-RIGHT Bits 10-8 (000)
7-3 2-0
Reserved Playback Window X-RIGHT Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-25
MR2E/AE
7 PB 1 PB 2
Playback Window Y-TOP Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 2Eh/AEh shadowed for each playback engine at MR2E, and cross-shared for the other at MRAE
Playback Window 1 Y-TOP Bits 7-0 (0000:0000) Playback Window 2 Y-TOP Bits 7-0 (0000:0000)
7-0
Playback Window Y-TOP Bits 7-0
MR2F/AF
7 PB 1 PB 2
Playback Window Y-TOP High Register
6 5 Reserved (0000:0) Reserved (0000:0) 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 2Fh/AFh shadowed for each playback engine at MR2F, and cross-shared for the other at MRAF
Playback Window 1 Y-TOP Bits 10-8 (000) Playback Window 2 Y-TOP Bits 10-8 (000)
7-3 2-0
Reserved Playback Window Y-TOP Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
16-26
Multimedia Registers
MR30/B0
7 PB 1 PB 2
Playback Window Y-BOTTOM Low Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 30h/B0h shadowed for each playback engine at MR30, and cross-shared for the other at MRB0
Playback Window 1 Y-BOTTOM Bits 7-0 (0000:0000) Playback Window 2 Y-BOTTOM Bits 7-0 (0000:0000)
7-0
Playback Window Y-BOTTOM Bits 7-0
MR31/B1
7 PB 1 PB 2
Playback Window Y-BOTTOM High Register
6 5 Reserved (0000:0) Reserved (0000:0) 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 31h/B1h shadowed for each playback engine at MR31, and cross-shared for the other at MRB1
Playbk Window 1 Y-BOTTOM Bits 10-8 (000) Playbk Window 2 Y-BOTTOM Bits 10-8 (000)
7-3 2-0
Reserved Playback Window Y-BOTTOM Bits 10-8
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-27
MR32/B2
7 PB 1 PB 2
H-ZOOM Register
6 5 H-ZOOM (0000:00) H-ZOOM (0000:00) 4 3 2 1 Reserved (00) Reserved (00) 0
read/write at I/O address 3D3h with index at address 3D2h set to 32h/B2h shadowed for each playback engine at MR32, and cross-shared for the other at MRB2
7-2
H-ZOOM When enabled by setting bit 2 of the Playback Control 1 Register (MR1E) to 1, these six bits are used to specify the zoom factor by which the playback image is magnified. Zoom factor = 100h / ((value of bits 7 to 2 of this register) * 4) Examples of programmed values:
Bits 765432 100000 010000 001000 Resulting Zoom Factor Magnify by 2 Magnify by 4 Magnify by 8
1-0
Reserved These bits always return the value of 0 when read.
MR33/B3
7 PB 1 PB 2
V-ZOOM Register
6 5 V-ZOOM (0000:00) V-ZOOM (0000:00) 4 3 2 1 Reserved (00) Reserved (00) 0
read/write at I/O address 3D3h with index at address 3D2h set to 33h/B3h shadowed for each playback engine at MR33, and cross-shared for the other at MRB3
7-2
V-ZOOM When enabled by setting bit 3 of the Playback Control 1 Register (MR1E) to 1, these six bits are used to specify the zoom factor by which the playback image is magnified. Zoom factor = 100h / ((value of bits 7 to 2 of this register) * 4) Examples of programmed values:
Bits 765432 100000 010000 001000 Resulting Zoom Factor Magnify by 2 Magnify by 4 Magnify by 8
1-0
Reserved These bits always return the value of 0 when read.
efmp69030 Databook
Revision 1.3 11/24/99
16-28
Multimedia Registers
MR34/B4
7 PB 1 PB 2
Playback Line Display Width Register
6 5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 34h/B4h shadowed for each playback engine at MR34, and cross-shared for the other at MRB4
Playback Engine 1 Line Display Width Bits 7-0 (0000:0000) Playback Engine 2 Line Display Width Bits 7-0 (0000:0000)
7-0
Playback Line Display Width Bits 7-0 If bit 6 of the Playback Control 3 Register (MR0C) is set to 1, then this register specifies the number of quadwords out of a horizontal line's worth of video data that is actually played back, starting at the left-most edge of the video playback window. This value is calculated as follows: ( (width of line in pixels) / (number of pixels per quadwords) ) - 1.
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-29
MR3C/BC
7 PB 1 PB 2 LSB Disable (0) LSB Disable (0)
Color Key Control Register
6 16-Bit Overlay (0) 16-Bit Overlay (0) 5 Blank Display (0) Blank Display (0) 4 Reserved (0:0) Reserved (0:0) 3 2 XY Rectangle (0) XY Rectangle (0) 1 Color Key (0) Color Key (0) 0 Video Overlay (0) Video Overlay (0)
read/write at I/O address 3D3h with index at address 3D2h set to 3Ch/BCh shadowed for each playback engine at MR3C, and cross-shared for the other at MRBC
7
LSB (Bit 0) disable 0: Normal "Blue bit 0" 1: Red, green, and blue bit 0 is forced to 0 at MMUX output (for masking display of key when using 16/24 bit overlay key). 16-bit Overlay Key 0: Normal color key 1: Color key "Green_7" is routed to "Blue_0" Blank Display 0: Graphics and video playback NOT blanked 1: Graphics and video playback blanked Reserved XY Rectangle Enable 0: XY Rectangular Region off 1: XY Rectangular Region enabled Color Key Enable 0: Color Key off 1: Color Key enabled Video Overlay Enable 0: Graphics only, if no video playback 1: Video Playback Window enabled
6
5
4-3 2
1
0
efmp69030 Databook
Revision 1.3 11/24/99
16-30
Multimedia Registers
MR3D/BD-3F/BF
7 PB 1 PB 2 6
Color Key Registers
5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 3Dh/8Dh-3Fh/BFh shadowed for each playback engine at MR3D-MR3F, and cross-shared for the other at MRBD-MRBF
Playback Engine 1 Color Keys Playback Engine 2 Color Keys
MR3D/BD: Red, 7-0
MR3E/BE: Green,
MR3F/BF: Blue
Red/Green/Blue Color Keys 0: Use the corresponding color key 1: Do not use color key
efmp69030 Databook
Revision 1.3 11/24/99
Multimedia Registers
16-31
MR40/C0-42/C2
7 PB 1 PB 2 6
Color Key Mask Registers
5 4 3 2 1 0
read/write at I/O address 3D3h with index at address 3D2h set to 40h/C0h-42h/C2h shadowed for each playback engine at MR40-MR42, and cross-shared for the other at MRC0-MRC2
Playback Engine 1 Color Key Masks Playback Engine 2 Color Key Masks
MR40/C0: Red Mask, 7-0
MR41/C1: Green Mask,
MR42/C2: Blue Mask
Red/Green/Blue Color Key Masks 0: Use the corresponding color key 1: Do not use color key
The table below describes the bits and values for the color key registers in different graphics modes. Table 16-2: Table 16-2: Color Key bit assignments:
Masks Display Mode 4-Bit Indexed 8-Bit Indexed 15-Bit RGB 16-Bit RGB 24-Bit RGB 16-Bit Key 24-Bit Key Red Bits 7-0 Green Bits 6-0 Green Bits 7-0 Green Bits 7-0 Green Bit 7 Blue Bits 7-0 R_Key G_Key B_Key Blue Bits 3-0 Blue Bits 7-0 Blue Bits 7-0 Blue Bits 7-0 Blue Bits 7-0 R_Key FF FF FF FF 00 FF FF G_Key FF FF 80 00 00 7F FF B_Key F0 00 00 00 00 FF FE
Note: Color Key bit assignments:
In 15 Bit RGB (5:5:5) Mode: RED Bits 7-3 = G_Key Bits 6-2 G_Key Bits 1-0, B_Key Bits 7-5 B_Key Bits 4-0 In 16 Bit RGB (5:6:5) Mode: RED Bits 7-3 = G_Key Bits 7-3
GREEN Bits 7-3= BLUE Bis 7-3 =
GREEN Bits 7-2= G_Key Bits 2-0, B_Key Bits 7-5 BLUE Bits 7-3 = B_Key Bits 4-0
efmp69030 Databook
Revision 1.3 11/24/99
16-32
Multimedia Registers
MR43
7 A B
Display Scanline Count Low
6 Reserved (0000) Reserved (0000) 5 4 3 2 1 0
read/write at I/O address 3D3h with 3D2h set to index 43h shadowed for pipelines A and B
Pipeline A Display Scanline Count Bits 11-8 (0000) Pipeline B Display Scanline Count Bits 11-8 (0000)
7-4 3-0
Reserved These bits always return the value of 0 when read. Display Line Count Bits 11-8 These are the upper 4 of 12 bits identifying the scanline currently being drawn on the display by the given pipeline.
MR44
7 A B
Display Line Count Low
6 5 4 3 2 1 0
read/write at I/O address 3D3h with 3D2h set to index 43h shadowed for pipelines A and B
Pipeline A Display Scanline Count Bits 7-0 (0000) Pipeline B Display Scanline Count Bits 7-0 (0000)
7-0
Display Line Count Bits 7-0 These are the lower 8 of 12 bits identifying the scanline currently being drawn on the display by the given pipeline.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers
17-1
Chapter 17 BitBLT Registers
Introduction
These registers exist in the upper memory space of the host bus. The BitBLT registers exist at an offset of 4MB from the base address of the upper memory space. Table 17-1:
Name BR00 BR01 BR02 BR03 BR04 BR05 BR06 BR07 BR08 BR09 BR0A
BitBLT Registers
Access read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Offset 400000 & C00000 400004 & C00004 400008 & C00008 40000C & C0000C 400010 & C00010 400014 & C00014 400018 & C00018 40001C & C0001C 400020 & C00020 400024 & C00024 400028 & C00028
Function Source and Destination Span Register Pattern/Source Expansion Background Color & Transparency Key Register Pattern/Source Expansion Foreground Color Register Monochrome Source Control Register BitBLT Control Register Pattern Address Register Source Address Register Destination Address Register Destination Width & Height Register Source Expansion Background Color & Transparency Key Register Source Expansion Foreground Color Register
efmp69030 Databook
Revision 1.3 11/24/99
17-2
BitBLT Registers
BR00
31 A & B 15 A & B
Source and Destination Span Register
30 Reserved (000) 29 28 27 26 25 24 23 22 21 20 19 18 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 400000 and C00000 shared by both pipelines A and B
Destination Span (x:xxxx:xxxx:xxxx)
14 Reserved (000)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Source Span (x:xxxx:xxxx:xxxx)
31-29 28-16
Reserved These bits always return 0 when read. Destination Span These 13 bits specify the span from the first byte in a scanline's worth of destination data to the first byte in the next scanline's worth. In other words, these bits specify the amount by which the destination address specified in BR07 should be incremented after a scanline's worth of destination data has been written to the destination in order to point to where the first byte in the next scanline's worth of destination data should be written. If the destination data is to be contiguous (i.e., it will be a single unbroken block of data where the last byte of a scanline's worth of data is immediately followed by the first byte of the next scanline's worth), then the value of this span should be set equal to the number of bytes in each scanline's worth of destination data.
15-13 12-0
Reserved These bits always return 0 when read. Source Span These 13 bits are used only when color source data is being used as an input in a BitBLT operation. If the source data is monochrome, or no source data is to be used, then the BitBLT engine will ignore the value carried by these bits. When color source data is read from the frame buffer, these 13 bits specify the span from the first byte in a scanline's worth of color source data to the first byte in the next scanline's worth. In other words, these bits specify the amount by which the source address specified in BR06 should be incremented after a scanline's worth of color source data has been read from the frame buffer in order to point to where the first byte in the next scanline's worth of color source data should be read. When the host CPU provides the color source data through the BitBLT data port, these 13 bits specify the number of bytes to be counted from the first byte in one scanline's worth of color source data to the first byte in the next scanline's worth. If the color source data is contiguous (i.e., it is a single unbroken block of data where the last byte of a scanline's worth of data is immediately followed by the first byte of the next scanline's worth), then the value of this span should be set equal to the number of bytes in each scanline's worth of color source data.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers
17-3
BR01 Pattern/Source Expansion Background Color & Transparency Key Register
doubleword-writable, byte/word/doubleword-readable at memory offsets 400004 and C00004 shared by both pipelines A and B
31 A & B 15 A & B 14 13 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved (0000:0000) 12 11 10 9 8 Pat/Src Expansion Background Color & Transparency Key Bits 23-16 (xxxx:xxxx) 7 6 5 4 3 2 1 0
Pattern/Source Expansion Background Color & Transparency Bits 15-0 (xxxx:xxxx:xxxx:xxxx)
31-24 23-0
Reserved These bits always return 0 when read. Pattern/Source Expansion Background Color & Transparency Key Bits 23-0 These 24 bits are used to specify the background color for the color expansion of either monochrome pattern data only, or both monochrome pattern data and monochrome source data (depending on the setting of bit 27 of BR03). When bit 27 of BR03 is set so that this register is used in the color expansion of monochrome pattern data only, BR09 is used to specify the background color for the color expansion of monochrome source data. These 24 bits are also optionally used to specify the key color for whichever form of color transparency is selected via bits 16-15 of BR04 (depending on the setting of bit 27 of BR03). Whether bits 7-0, 15-0 or 23-0 of this register are used in both the color expansion and color transparency processes depends upon the color depth to which the BitBLT engine has been set.
efmp69030 Databook
Revision 1.3 11/24/99
17-4
BitBLT Registers
BR02 Pattern/Source Expansion Foreground Color Register
doubleword-writable, byte/word/doubleword-readable at memory offsets 400008 and C00008 shared by both pipelines A and B
31 A & B 15 A & B 14 13 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved (0000:0000) 12 11 10 9 8 7 6 5 Pat/Src Expansion Foreground Color Bits 23-16 (xxxx:xxxx) 4 3 2 1 0
Pattern/Source Expansion Foreground Color Bits 15-0 (xxxx:xxxx:xxxx:xxxx)
31-24 23-0
Reserved These bits always return 0 when read. Pattern/Source Expansion Foreground Color Bits 23-0 These 24 bits are used to specify the foreground color for the color expansion of either monochrome pattern data only, or both monochrome pattern data and monochrome source data (depending on the setting of bit 27 of BR03). When bit 27 of BR03 is set so that this register is used in the color expansion of monochrome pattern data only, BR0A is used to specify the foreground color for the color expansion of monochrome source data. Whether bits 7-0, 15-0 or 23-0 of this register are used in the color expansion process depends upon the color depth to which the BitBLT engine has been set.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers
17-5
BR03
31 A & B 15 A & B
Monochrome Source Control Register
30 29 28 27 Src Exp (x) 12 11 26 25 24 23 22 21 20 19 18 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 40000C and C0000C shared by both pipelines A and B
Reserved (0000) 14 13 Mono Src Align (xxx) 10 9 8 7 Reserved (00) 6 5 4 Monochrome Source Data Initial Discard (xx:xxxx) 3 2 1 0
Reserved (00)
Monochrome Source Data Right Clipping (xx:xxxx)
Reserved (00)
Monochrome Source Data Left Clipping (xx:xxxx)
31-28 27
Reserved These bits always return 0 when read. Monochrome Source Expansion Color Register Select 0: This causes the background and foreground colors for the color expansion of monochrome source data to be specified by BR01 and BR02, respectively. 1: This causes the background and foreground colors for the color expansion of monochrome source data to be specified by BR09 and BR0A, respectively. Monochrome Source Scanline Data Alignment Note: These bits are used only when the source data is monochrome. These 3 bits are used to configure the BitBLT engine for the byte alignment of each scanline's worth of monochrome source data during a BitBLT operation, as each scanline's worth of monochrome source data is received. Refer to the section describing the BitBLT engine for further details concerning the requirements for how monochrome source data must be organized.
Bit 26 25 24 000 001 010 011 100 101 110 111 Specified Monochrome Source Data Alignment Reserved Bit-Aligned Byte-Aligned Word-Aligned Doubleword-Aligned Quadword-Aligned Reserved Reserved
26-24
efmp69030 Databook
Revision 1.3 11/24/99
17-6 23-22 21-16
BitBLT Registers Reserved These bits always return 0 when read. Monochrome Source Data Initial Discard Note: These bits are used only when the source data is monochrome. These 6 bits are used to specify how many bits (up to 63 bits) of monochrome source data should be skipped over in the first quadword of source data in order to reach the first bit of valid or desired monochrome source data. These bits are normally used to clip one or more of the first scanline's worth of monochrome source data, (i.e. clipping monochrome source data from the top).
15-14 13-8
Reserved These bits always return 0 when read. Monochrome Source Data Right Clipping Note: These bits are used only when the source data is monochrome. These 6 bits are used to specify how many bits (up to 63 bits) of monochrome source data should be discarded from the end of each scanline's worth of valid or desired monochrome source data. These bits are normally used to clip monochrome source data from the right.
7-6 5-0
Reserved These bits always return 0 when read. Source Data Left Clipping Note: These bits are used only when the source data is monochrome. These 6 bits are used to indicate how many bits (up to 63 bits) of monochrome source data should be discarded from the beginning of each scanline's worth of valid or desired monochrome source data. These bits are normally used to clip the monochrome source data from the left.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers
17-7
BR04
31 A & B BB Stat (0) 15 A & B Tran Sel (0)
BitBLT Control Register
30 29 28 Reserved (000:00) 14 13 12 Src Dep (0) 11 Rsvd (0) 10 Src Sel (0) 27 26 25 24 23 Dep Ctrl (0) 7 22 21 20 19 Sol Pat (0) 3 18 Pat Dep (0) 2 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 400010 and C00010 shared by both pipelines A and B
BitBLT Eng Color Depth (00) 9 8 Pattern Vertical Alignment (000) 6 5 4 Pat Tran Mask Sel (0) (0) 1 0
Tran Src Enl Mask (0) (0)
Starting Point Select (00)
Bit-Wise Operation Select (00h)
31
30-26 25-24
BitBLT Engine Status Note: This bit is read-only -- writes to this bit are ignored. 0: Indicates that the BitBLT engine is idle. 1: Indicates that the BitBLT engine is busy. Reserved These bits always return 0 when read. BitBLT Engine Color Depth When bit 23 of this register is set to 1, these 2 bits configure the color depth of the BitBLT engine. If bit 23 of this register is set to 0, then this function is performed by bits 5 and 4 of XR20.
Bit 25 24 00 01 10 11 BitBLT Engine Color Depth Selected 8 bits per pixel (1 byte per pixel) This is the default after reset. 16 bits per pixel (2 bytes per pixel) 24 bits per pixel (3 bytes per pixel) Reserved
The choice of color depth configures the BitBLT engine to work with one, two or three bytes per pixel. This directly affects the number of bytes of graphics data that the BitBLT engine will read and write for a given number of pixels. In the case of monochrome source or pattern data, this setting directly affects the color depth into which such monochrome data will be converted during the color expansion process. It is strongly recommended that, when possible, the color depth of the BitBLT engine be set to match the color depth to which the rest of graphics system has been set. However, if the rest of the graphics system has been set to a color depth that is not supported by the BitBLT engine, then it is strongly recommended that the BitBLT engine not be used. See the section on the BitBLT engine for more information.
efmp69030 Databook
Revision 1.3 11/24/99
17-8 23
BitBLT Registers BitBLT Engine Color Depth Control Select 0: Bits 5 and 4 of the BitBLT Configuration Register (XR20) are used to configure the BitBLT engine for one of three color depths. This is the default after reset. 1: Bits 25 and 24 of this register are used to configure the BitBLT engine for one of three color depths. Pattern Vertical Alignment Specifies which scanline's worth (i.e., which 1 of the 8 horizontal rows) of the 8x8 pattern data will appear in the first scanline's worth of the destination output data. Depending on the location of the destination, the upper left corner of the upper left tile of the pattern data is usually aligned with the upper left corner of the destination output data as the pattern data is tiled into the destination. The BitBLT engine determines the horizontal alignment of the leftmost tiles of pattern data relative to the destination using the lower order bits of the destination address specified in BR07. However, the vertical alignment relative to the destination must be specified using these 3 bits. Solid Pattern Select Note: This bit applies only when the pattern data is monochrome (determined by bit 18 of this register). 0: Causes monochrome pattern data to actually be read and used as is normal, if indeed monochrome pattern data is being used as an input to a BitBLT operation. 1: Causes the BitBLT engine to forgo the process of reading the pattern data. Instead, the presumption is made that all of the bits of the pattern data are set to 0. The pattern operand for all bit-wise operations is forced to the background color specified in BR01.
22-20
19
18
Pattern Color Depth 0: Specifies that the pattern data is in color and therefore can have a color depth of 8, 16, or 24 bits per pixel. 1: Specifies that the pattern data is monochrome and therefore has a color depth of 1 bit per pixel. Monochrome Pattern Write-Masking Note: This bit applies only when the pattern data is monochrome (determined by bit 18 of this register). This bit enables a form of per-pixel write-masking in which monochrome pattern data is used as a pixel mask that controls which pixels at the destination will be written to by the BitBLT engine. 0: This disables the use of monochrome pattern data as a write mask, allowing normal operation of the BitBLT engine with regard to the use of monochrome pattern data. 1: Wherever a bit in monochrome pattern data carries the value of 0 the byte(s) of the corresponding pixel at the destination are NOT written, thereby preserving any data already carried by those bytes.
17
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers 16-15 Color Transparency Select These 2 bits are used to select the type of color transparency to be performed.
17-9
When color transparency is enabled by setting bit 14 of this register to 1, the color value carried within bits 23-0 of either BR01 or BR09 is used as a key color to mask the writing of pixel data to the destination on a per-pixel basis. Before each pixel at the destination is written, a comparison is made between this key color and another color, and whether or not that given pixel at the destination will actually be written depends upon the result of that comparison. Whether BR01 or BR09 is used to supply the key color depends on the setting of bit 27 of BR03 since the same register that is used to supply the key color for color transparency also happens to be used to supply the background color for monochrome-to-color expansion. Also, depending on the type of color transparency selected, the other color value to which the key color is compared may be the color value resulting from the bit-wise operation selected via bits 7-0 of this register.
Bit 16 15 00 Form of Per-Pixel Color Comparison Selected The color value carried by bits 23-0 of either BR01 or BR09 is compared to the color value resulting from the bit-wise operation being performed for the current pixel. If these two color values are NOT the same, then the byte(s) for the current pixel at the destination will be written with the color value resulting from the bit-wise operation. The color value carried by bits 23-0 of either BR01 or BR09 is compared to the color value already specified in the byte(s) for the current pixel at the destination. If these two color values are NOT the same, then the byte(s) for the current pixel at the destination will be written with the color value resulting from the bit-wise operation. The color value carried by bits 23-0 of either BR01 or BR09 is compared to the color value resulting from the bit-wise operation being performed for the current pixel. If these two color values ARE the same, then the byte(s) for the current pixel at the destination will be written with the color value resulting from the bit-wise operation. The color value carried by bits 23-0 of either BR01 or BR09 is compared to the color value already specified in the byte(s) for the current pixel at the destination. If these two color values ARE the same, then the byte(s) for the current pixel at the destination will be written with the color value resulting from the bit-wise operation.
01
10
11
Note: Color transparency can be used only when the BitBLT engine is set to a color depth of 8 or 16 bits per pixel, but not 24 bits per pixel. If the BitBLT engine has been set to a color depth of 24 bits per pixel, then bit 14 of this register should always remain set to 0 to disable color transparency.
efmp69030 Databook
Revision 1.3 11/24/99
17-10 14
BitBLT Registers Color Transparency Enable These bit is used to enable or disable color transparency. When color transparency is enabled, the color value carried within bits 23-0 of either BR01 or BR09 is used as a key color to mask the writing of pixel data to the destination on a perpixel basis. Before each pixel at the destination is written, a comparison is made between this key color and another color, and whether or not that given pixel at the destination will actually be written depends upon the result of that comparison. Whether BR01 or BR09 is used to supply the key color depends on the setting of bit 27 of BR03 since the same register that is used to supply the key color for color transparency also happens to be used to supply the background color for monochrome-to-color expansion. Also, depending on the type of color transparency selected via bits 16-15 of this register, the other color value to which the key color is compared may be the color value resulting from the bit-wise operation selected via bits 7-0 of this register. 0: Disables color transparency. 1: Enables color transparency. Note: Color transparency can be used only when the BitBLT engine is set to a color depth of 8 or 16 bits per pixel, but not 24 bits per pixel. If the BitBLT engine has been set to a color depth of 24 bits per pixel, then this bit should always remain set to 0 to disable color transparency.
13
Monochrome Source Write-Masking Note: This bit applies only when the source data is monochrome (determined by bit 12 of this register). This bit enables a form of per-pixel write-masking in which monochrome source data is used as a pixel mask that controls which pixels at the destination will be written to by the BitBLT engine. 0: This disables the use of monochrome source data as a write mask, allowing normal operation of the BitBLT engine with regard to the use of monochrome source data. 1: Wherever a bit in monochrome source data carries the value of 0, the byte(s) of the corresponding pixel at the destination are NOT written, thereby preserving any data already carried by those bytes.
12
Source Color Depth 0: Specifies that the source data is in color, and therefore, can have a color depth of 8, 16, or 24 bits per pixel. 1: Specifies that the source data is monochrome, and therefore, has a color depth of 1 bit per pixel. This setting should be used only if bit 8 of this register is set to 0. Note: This bit must be set to 0 whenever a bit-wise operation is selected (using bits 7-0 of this register) that does not use source data.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers 11 10 Reserved (Writable) This bit should always be written with the value of 0.
17-11
Source Select 0: Configures the BitBLT engine to read the source data from the frame buffer at the location specified in BR06. 1: Configures the BitBLT engine to accept the source data from the host CPU via the BitBLT data port. The host CPU provides the source data by performing a series of memory write operations to the BitBLT data port. Starting Point Select These two bits are used to select which of the four corners to use as the starting point in reading and writing graphics data in a BitBLT operation. Normally, the upper left corner is used. However, situations involving an overlap of source and destination locations (this usually occurs when the source and destination locations are both on-screen) often require the use of a different corner as a starting point. It should be remembered that the addresses specified for each piece of graphics data used in a BitBLT operation must point to the byte(s) corresponding to whichever pixel is at the selected starting point. If the starting point is changed, then these addresses must also be changed. See the chapter on the BitBLT engine for more information.
Bit 98 Corner Selected as the Starting Point
9-8
0 0 Upper Left Corner -- This is the default after reset. 0 1 Upper Right Corner 1 0 Lower Left Corner 1 1 Lower Right Corner
7-0
Bit-Wise Operation Select These 8 bits are meant to be programmed with an 8-bit code that selects which one of 256 possible bit-wise operations is to be performed by the BitBLT engine during a BitBLT operation. These 256 possible bit-wise operations and their corresponding 8-bit codes are designed to be compatible with the manner in which raster operations are specified in the standard BitBLT parameter block normally used in the Microsoft Windows environment, without translation. See the section on the BitBLT engine for more information. Note: Bit 12 of this register must be set to 0 whenever a bit-wise operation is selected that does not use source data.
efmp69030 Databook
Revision 1.3 11/24/99
17-12
BitBLT Registers
BR05
31 A & B 15 A & B
Pattern Address Register
30 29 28 27 26 Reserved (0000:0000:000) 14 13 12 11 10 9 8 7 6 5 4 3 25 24 23 22 21 20 19 18 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 400014 and C00014 shared by both pipelines A and B
Pattern Address Bits 20-16 (x:xxxx) 2 1 Reserved (000) 0
Pattern Address Bits 15-3 (xxxx:xxxx:xxxx:x)
31-21 20-3
Reserved (Writable) These bits should always be written with the value of 0. Pattern Address These bits specify the starting address of the pattern data within the frame buffer as an offset from the beginning of the frame buffer to where the first byte of pattern data is located. The pattern data is always an 8x8 array of pixels that is always stored in frame buffer memory as a single contiguous block of bytes. The pattern data must be located on a boundary within the frame buffer that is equivalent to its size, and its size depends on the pattern data's color depth. The color depth may be 1 bit per pixel if the pattern data is monochrome or it may be 8, 16, or 24 bits per pixel if the pattern data is in color (the color depth of a color pattern must match the color depth to which the BitBLT engine has been set). Monochrome patterns require 8 bytes, and so the pattern data must start on a quadword boundary. Color patterns of 8, 16, and 24 bits per pixel color depth must start on 64-byte, 128-byte, and 256-byte boundaries, respectively. Note: In the case of 24 bits per pixel, each row of 8 pixels of pattern data takes up 32 consecutive bytes, not 24. The pattern data is formatted so that for each row there is a block of 8 sets of 3 bytes (each set corresponding to one of the 8 pixels), followed by a block of the 8 extra bytes. When the BitBLT engine reads 24 bit-per-pixel pattern data, it will read only the first 24 bytes of each row of pattern data, picking up only the 8 sets of 3 bytes for the 8 pixels in that row, and entirely ignoring the remaining 8 bytes.
2-0
Reserved These bits always return 0 when read.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers
17-13
BR06
31 A & B 15 A & B
Source Address Register
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 400018 and C00018 shared by both pipelines A and B
Reserved (0000:0000:000) Source Address Bits 20-16 (x:xxxx)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Source Address Bits 15-0 (xxxx:xxxx:xxxx:xxxx)
Important: This register should never be read while the BitBLT engine is busy. 31-21 20-0 Reserved (Writable) These bits should always be written with the value of 0. Source Address When the source data is located within the frame buffer, these bits are used to specify the starting address of the source data within the frame buffer as an offset from the beginning of the frame buffer to where the first byte of source data is located. When the source data is provided by the host CPU through the BitBLT data port and that source data is in color, only bits 2-0 are used and the upper bits are ignored. These lower 3 bits are used to indicate the position of the first valid byte within the first quadword of the source data. When the source data is provided by the host CPU through the BitBLT data port and that source data is monochrome, the BitBLT engine ignores this register entirely.
efmp69030 Databook
Revision 1.3 11/24/99
17-14
BitBLT Registers
BR07
31 A & B 15 A & B
Destination Address Register
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 40001C and C0001C shared by both pipelines A and B
Reserved (0000:0000:000) Destination Address Bits 20-16 (x:xxxx)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Destination Address Bits 15-0 (xxxx:xxxx:xxxx:xxxx)
Important: This register should never be read while the BitBLT engine is busy. 31-21 20-0 Reserved (Writable) These bits should always be written with the value of 0. Destination Address These bits are used to specify the starting address of the destination location within the frame buffer as an offset from the beginning of the frame buffer to where the first byte of the destination location. The destination location is the location from which destination input data (if used) will be read, and it is where the destination output data will be written.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers
17-15
BR08
31 A & B
Destination Width & Height Register
30 Reserved (000) 29 28 27 26 25 24 23 22 21 20 19 18 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 400020 and C00020 shared by both pipelines A and B
Destination Scanline Height (0:0000:0000:0000)
15 A & B
14 Reserved (000)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Destination Byte Width (0:0000:0000:0000)
Important: This register should never be read while the BitBLT engine is busy. 31-29 28-16 Reserved These bits always return 0 when read. Destination Scanline Height These 13 bits specify the height of the destination input and output data in terms of the number of scanlines. Reserved These bits always return 0 when read. Destination Byte Width These 13 bits specify the width of the destination input and output data in terms of the number of bytes per scanline's worth. The number of pixels per scanline into which this value translates depends upon the color depth to which the BitBLT engine has been set.
15-13 12-0
efmp69030 Databook
Revision 1.3 11/24/99
17-16
BitBLT Registers
BR09 Source Expansion Background Color & Transparency Key Register
doubleword-writable, byte/word/doubleword-readable at memory offsets 400024 and C00024 shared by both pipelines A and B
31 A & B 15 A & B 14 13 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved (0000:0000) 12 11 10 9 8 Src Expansion Background Color & Transparency Key Bits 23-16 (xxxx:xxxx) 7 6 5 4 3 2 1 0
Source Expansion Background Color & Transparency Key Bits 15-0 (xxxx:xxxx:xxxx:xxxx)
31-24 23-0
Reserved These bits always return 0 when read. Source Expansion Background Color & Transparency Key Bits 23-0 These 24 bits are optionally used to specify the background color for the color expansion of monochrome source data (depending on the setting of bit 27 of BR03). When bit 27 of BR03 is set so that this register is used in the color expansion of monochrome source data, BR01 is used to specify the background color for the color expansion of monochrome pattern data. These 24 bits are also optionally used to specify the key color for whichever form of color transparency is selected via bits 16-15 of BR04 (depending on the setting of bit 27 of BR03). Whether bits 7-0, 15-0 or 23-0 of this register are used in both the color expansion and color transparency processes depends upon the color depth to which the BitBLT engine has been set.
efmp69030 Databook
Revision 1.3 11/24/99
BitBLT Registers
17-17
BR0A
31 A & B 15 A & B 14 30
Source Expansion Foreground Color Register
29 28 27 26 25 24 23 22 21 20 19 18 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 400028 and C00028 shared by both pipelines A and B
Reserved (0000:0000) 13 12 11 10 9 8 7 6 5 Source Expansion Foreground Color Bits 23-16 (xxxx:xxxx) 4 3 2 1 0
Source Expansion Foreground Color Bits 15-0 (xxxx:xxxx:xxxx:xxxx)
31-24 23-0
Reserved These bits always return 0 when read. Pattern/Source Expansion Foreground Color Bits 23-0 These 24 bits are optionally used to specify the foreground color for the color expansion of monochrome source data (depending on the setting of bit 27 of BR03). When bit 27 of BR03 is set so that this register is used in the color expansion of monochrome source data, BR02 is used to specify the foreground color for the color expansion of monochrome pattern data. Whether bits 7-0, 15-0 or 23-0 of this register are used in the color expansion process depends upon the color depth to which the BitBLT engine has been set.
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17-18
BitBLT Registers
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Memory-Mapped Wide Extension Registers
18-1
Chapter 18
Memory-Mapped Wide Extension Registers
Introduction
The video decoder registers are 32-bit memory-mapped registers that exist in the upper memory space that the graphics controller occupies on the host bus. Refer to chapter on address maps for more information. These registers exist at an offset of 0x400600h from the base address of the memory space. Table 18-1:
Name ER00 ER01 ER03
Memory-Mapped Wide Extension Registers
Function Central Interrupt Control Register Central Interrupt Pending/Acknowledge Register Miscellaneous Function Register Access read: byte/word/Dword write: Dword read: byte/word/Dword write: Dword read: byte/word/Dword write: Dword Offset 0x400600 & 0xC00600 0x400604 & 0xC00604 0x40060C & 0xC0060C
efmp69030 Databook
Revision 1.3 11/24/99
18-2
Memory-Mapped Wide Extension Registers
ER00
31
Central Interrupt Control Register
30 29 28 27 26 25 24 Reserved (00:0000:0000:0) 13 12 11 10 Reserved (00:0000:0) 9 8 7 6 V Cap VSync (0) 5 4 3 23 22 21 20 19 18 Pipe B V Blnk (0) 2 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 0x400600 and 0xC00600 shared by both pipelines A and B
A BBLT BBLT & Idle Queue B (0) (0) 15 A & B 14 Reserved (00) 1 0
Rsvd Pipe A V Blnk (0) (0)
Reserved (00:0000)
31
BitBLT Engine Idle Interrupt Output Enable 0: No hardware interrupt is output to the host when the BitBLT engine becomes idle after performing a BitBLT operation. 1: Causes a hardware interrupt to be output to the host when the BitBLT engine becomes idle after performing a BitBLT operation. BitBLT Engine Command Queue Low Interrupt Pending 0: Since this bit was last cleared, no interrupt has been sourced as a result of the command queue used by the BitBLT engine going below the low watermark. 1: An interrupt was sourced as a result of the command queue used by the BitBLT engine going below the low watermark. Writing the value of 1 to this bit will clear it to 0 (writing the value of 0 to this bit has no effect and will be ignored). Reserved These bits always return the value of 0 when read. Pipeline B Vertical Blanking Period Interrupt Output Enable 0: No hardware interrupt is output to the host when the last pixel of the last scan line within the active display area is drawn on pipeline B. 1: Causes a hardware interrupt to be output to the host when the last pixel of the last scan line within the active display area is drawn on pipeline B. This bit always return the value of 0 when read. Reserved These bits always return the value of 0 when read. Pipeline A Vertical Blanking Period Interrupt Output Enable 0: No hardware interrupt is output to the host when the last pixel of the last scan line within the active display area has been drawn on pipeline A. 1: Causes a hardware interrupt to be output to the host when the last pixel of the last scan line within the active display area has been drawn on pipeline A. Reserved These bits always return the value of 0 when read. Video Capture Vertical Sync Interrupt Output Enable 0: No hardware interrupt is output to the host at the start of each vertical sync pulse from the acquisition data source. 1: Causes a hardware interrupt to be output to the host at the start of each vertical sync pulse from the acquisition data source. Reserved These bits always return the value of 0 when read. Revision 1.3 11/24/99
30
29-19 18
17-15 14
13-7 6
5-0
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ER01
31
Central Interrupt Pending/Acknowledge Register
30 29 28 27 26 25 24 Reserved (00:0000:0000:0) 23 22 21 20 19 18 Pipe B V Blnk (0) 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 0x400604 and 0xC00604 shared by both pipelines A and B
A BBLT BBLT & Idle Queue B (0) (0) Reserved (00)
15 A & B
14
13
12
11
10 Reserved (00:0000:0)
29
8
7
6 V Cap VSync (0)
5
4
3
2
1
0
Rsvd Pipe A V Blnk (0) (0)
Reserved (00:0000)
31
BitBLT Engine Idle Interrupt Pending 0: Since this bit was last cleared, no interrupt has been pending as a result of the BitBLT engine becoming idle after performing a BitBLT operation. 1: An interrupt is pending as a result of the BitBLT engine becoming idle after performing a BitBLT operation. Writing the value of 1 to this bit will clear it to 0 (writing the value of 0 to this bit has no effect and will be ignored). BitBLT Engine Empty Interrupt Pending 0: Since this bit was last cleared, no interrupt has been pending as a result of the BitBLT engine and its pipe becoming empty, both blitter engines becoming idle and the command parser processing a flush command. 1: An interrupt is pending as a result of the BitBLT engine and its pipe becoming empty, both blitter engines becoming idle and the command parser processing a flush command. Writing the value of 1 to this bit will clear it to 0 (writing the value of 0 to this bit has no effect and will be ignored). Reserved These bits always return the value of 0 when read. Pipeline B Vertical Blanking Period Interrupt Pending 0: Since this bit was last cleared, no interrupt has been pending as a result of the drawing of the last scan line within the active display area on pipeline B. 1: An interrupt is pending as a result of the drawing of the last scan line within the active display area on pipeline B. Writing the value of 1 to this bit will clear it to 0 (writing the value of 0 to this bit has no effect and will be ignored).
30
29-19 18
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Memory-Mapped Wide Extension Registers Reserved These bits always return the value of 0 when read. Pipeline A Vertical Blanking Period Interrupt Pending 0: Since this bit was last cleared, no interrupt has been pending as a result of the drawing of the last scan line within the active display area on pipeline A. 1: An interrupt is pending as a result of the drawing of the last scan line within the active display area on pipeline A. Writing the value of 1 to this bit will clear it to 0 (writing the value of 0 to this bit has no effect and will be ignored). Reserved These bits always return the value of 0 when read. Video Capture Vertical Sync Interrupt Pending 0: Since this bit was last cleared, no interrupt has been pending as a result of the start of a vertical sync pulse from the acquisition data source. 1: An interrupt is pending as a result of the start of a vertical sync pulse from the acquisition data source. Writing the value of 1 to this bit will clear it to 0 (writing the value of 0 to this bit has no effect and will be ignored). Reserved These bits always return the value of 0 when read.
13-7 6
5-0
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ER03
31 A & B
Miscellaneous Function Register
30 29 28 27 26 25 Reserved (0000:0000:0000:0) 24 23 22 21 20 19 18 Pipe B V Blnk (0) 17 16
doubleword-writable, byte/word/doubleword-readable at memory offsets 0x40060C and 0xC0060C shared by both pipelines A and B
Reserved (00)
15 A & B
14
13
12
11
10 Reserved (00:0000:0)
29
8
7
6 V Cap VSync (0)
5
4
3
2
1
0
Rsvd Pipe A V Blnk (0) (0)
Reserved (00:0000)
31-19 18
Reserved These bits always return the value of 0 when read. Pipeline B Display Vertical Blanking Period Interrupt Source Polarity 0: No inversion. 1: Inversion. Reserved These bits always return the value of 0 when read. Pipeline A Display Vertical Blanking Period Interrupt Source Polarity 0: No inversion. 1: Inversion. Reserved These bits always return the value of 0 when read. Video Capture Vertical Sync Interrupt Source Polarity 0: No inversion. 1: Inversion. Reserved These bits always return the value of 0 when read.
17-15 14
13-7 6
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Display Modes
A-1
Appendix A Display Modes
Introduction
This chapter lists tables for configuring the 69030 graphics accelerator for various CRT monitor and flat panel graphics and text display modes. The parameters detailed in the tables of this chapter define standard capabilities of the 69030 graphics accelerator when it is used with the Intel VGA BIOS. Consult with the appropriate BIOS vendor for information about display modes and parameters that are supported by BIOSs that are not from Intel. The following symbols and abbreviations are used for display modes in the following sections: - * + DSTN I L P Indicates CGA display mode (Table A-1 only.) EGA display mode. (Table A-1 only.) VGA display mode. (Table A-1 only.) Dual-scan STN flat panel Interlaced Linear mapped Page mapped
Note: Tables to be provided in a later revision.
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Display Modes
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Clock Generation
B-1
Appendix B Clock Generation
Introduction
Appendix B describes Clock Generation for the 69030 Dual HiQVideo Accelerator.
Clock Synthesizer
The graphics controller contains three complete phase-locked loops (PLLs) to synthesize the internal Dot Clock (DCLK) and Memory Clock (MCLK) from an externally supplied reference frequency. Each of the two clock synthesizer phase lock loops may be programmed to output frequencies ranging between 3MHz and the maximum specified operating frequency for that clock in increments not exceeding 0.5%. An external crystal-controlled oscillator (TTL) generates the reference frequency of 14.31818 MHz that is driven into the graphics controller on pin C3. The graphics controller can not generate the 14.31818 MHz reference frequency using only an external crystal.
Dot Clock (DCLK)
The dot clock is used as the basis for all display timings. The horizontal and vertical sync frequencies are derived by dividing down the dot clock. In borrowing from VGA parlance, there are said to be three dot clocks: DCLK0, DCLK1 and DCLK2. In truth, there is actually only a single PLL, but it can be configured with divisor values from any one of three sets of registers within the XRC0-XRCF group of registers, and these three groups of registers are referred to as if they were DCLK0, DCLK1 and DCLK2. Bits 3 and 2 of the Miscellaneous Output Register (MSR) are used to select which one of these 3 sets of registers will be used to supply the divisor values that the PLL will use in creating the dot clock at any given time. During reset, the first two sets of these registers (DCLK0 and DCLK1) default to values that specify the two standard VGA dot clocks of 25.175MHz and 28.322MHz, and normally the values in these first two sets of registers are not changed. The third set of registers (DCLK2) is used for all modes that are not of the VGA standard, i.e., the extended modes.
Memory Clock (MCLK)
The memory clock is used as the basis for all memory timings. It is normally set once following hardware reset, and is not normally modified again.
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Clock Generation
PLL Parameters
Each phase-locked loop consists of the elements shown in the figure below. The reference input frequency (14.31818MHz) is divided by N, a 8-bit programmable value. The output of the VCO is divided by 1 (or 4 via the VCO Loop Divider: VLD) and then further divided by M, another 8-bit programmable value. The phase detector compares the N and M results and adjusts the VCO frequency as needed to achieve frequency equality. When the loop has stabilized, the VCO frequency (FVCO) is related to the reference as follows: If VLD=1: or If VLD=4: (DCLK only) For VLD =1, the FVCO can be written as: FVCO = (FREF *M /N) The VCO output can be further divided by 1, 2, 4, 8, 16, or 32 (which is called Post Divisor: PD) to produce the final DCLK or MCLK used for video or memory timing. Therefore the output frequency is: FOUT = (FVCO)/PD By "fine tuning" the M/N ratio in each PLL, extremely small adjustments in the exact DCLK and MCLK frequencies can be achieved. The VCO itself is designed to operate in the range of 100MHz to 220 MHz. FVCO /M = FREF / N FVCO /4M = FREF / N.
REFCLK 14.3MHz
/ N
F VCO
Phase Detect Charge Pump & Filter VCO
(DCLK only)
/M VCO Loop Divide (VLD) (/4, /1)
Post Divisor (PD) /1, 2, 4, 8, 16, 32
F OUT
CLK
M counter = Program value M'+2 N counter = Program value N'+2
FVCO: VCO frequency (before post divisor) FOUT: Output frequency: (desired frequency)
Figure B-1: PLL Elements
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Programming the Clock Synthesizer
Below are the register tables for CLK0, CLK1, CLK2, and MCLK. Please see the block diagram for M, N, and Post Divide (PD). .
CLK0 M N VLD PD XRC0 XRC1 XRC3[2] XRC3[6:4] CLK2 M N VLD PD XRC8 XRC9 XRCB[2] XRCB[6:4] XRCE[6:4] CLK1 XRC4 XRC5 XRC7[2] XRC7[6:4] MCLK XRCC[7:0] XRCD[7:0]
DCLK Programming
For each DCLK, a new frequency should be programmed by following below sequence: 1) 2) 3) Program M Program N Program PD This will effectively change DCLK into the new frequency
MCLK Programming
For MCLK, a new frequency should be programmed by following the sequence below: 1) 2) 3) Program M Program N Program PD
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Clock Generation
Programming Constraints
The programmer must be aware of the following five programming constraints: 1 MHz FREF 83 MHz 150 KHz FREF /(N) 5 MHz 100 MHz FVCO 220 MHz 3 M 257 3 N 257 The constraints have to do with trade-offs between optimum speed with lowest noise, VCO stability and factors affecting the loop equation. The value of FVCO must remain between 100 MHz and 220 MHz inclusive. Therefore, for output frequencies below 100 MHz, FVCO must be brought into range by using the post-VCO Divisor. To avoid crosstalk between the VCOs, the VCO frequencies should not be within 0.5% of each other nor should their harmonics be within 0.5% of the other's fundamental frequency. The graphics controller's clock synthesizers will seek the new frequency as soon as it is loaded following a write to the control register. Any change in the post-divisor will take affect immediately. There is also the consideration of changing from a low frequency VCO value with a post-divide/1 (e.g., 100 MHz) to a high frequency / 4 (e.g., 220 MHz). Although the beginning and ending frequencies are close together, the intermediate frequencies may cause the graphics controller to fail in some environments. In this example, there will be a short-lived time during which the output frequency will be approximately 12.5 MHz. The graphics controller provides the mux for MCLK so it can select the fixed frequency (25.175 MHz) before programming a new frequency. Because of this, the bus interface may not function correctly if the MCLK frequency falls below a certain value. Register and memory accesses synchronized to MCLK may be too slow and violate the bus timing causing a watchdog timer error.
Programming Example
The following is an example of the calculations which are performed. Derive the proper programming word for a 25.175 MHz output frequency using a 14.31818 MHz reference frequency. Since 25.175 MHz < 100 MHz, quadruple it to 100.70 MHz to get FVCO in its valid range. Set the post divide (PD) divide by 4. Video Loop Divisor Selector (VLD) = 1 The result: FVCO = 100.70 = (14.31818 x M/N) M/N = 7.0330
Several choices for M and N are available:
M 211 204
N 30 29
FVCO 100.70 100.72
Error -0.00005 +0.00021
Choose (M, N) = (211, 30) for best accuracy. Therefore M is less than 255 and VLD = 1, P = 4.
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B-5
FREF / N = 157.3KHz XRC0 = 211 - 2 = 209 (D1h) XRC1= 30 - 2 = 28 (1Eh) XRC3= 0010 0100 = 24h
PCB Layout Considerations
Clock synthesizers, like most analog components, must be isolated from the noise that exists on a PCB power plane. Care must be taken not to route any high frequency digital signals in close proximity to the analog sections. Inside the graphics controller chip, the clocks are physically located in the lower left corner of the chip surrounded by low frequency input and output pins. This helps to minimize both internally and externally coupled noise. The memory clock and video clock power pins on the graphics controller chip each require similar RC filtering to isolate the synthesizers from the VCC plane and from each other. The filter circuit for each CVCCn/CGND pair is shown below:
VDD
10 + 0.1F
0.1F 47F
DCKVCC / MCKVCC DCKGND / MCKGND
The suggested method for layout assumes a multilayer board including VCC and GND planes. All ground connections should be made as close to the pin/component as possible. The CVCC trace should route from the graphics controller through the pads of the filter components. The trace should NOT be connected to the filter components by a stub. All components (particularly the nearest 0.1F capacitor) should be placed as close as possible to the graphics controller.
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Clock Generation
Vcc
GND GND C2 GND C3 DCKGND from graphics controller
C1
R1
GND
DCKVCC MCKVCC MCKGND R2 C5 GND C6
Vcc Vcc
GND C4
GND
Always pass the Vcc trace through the decoupling cap pad. Do not leave a stub as shown. C7
Note: Do not connect Vcc here. Force the trace through the decoupling cap pad.
GND
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Display Memory Bandwidth
The graphics controller's ability to support high performance Super VGA modes can be limited by display memory bandwidth as well as the maximum allowable DCLK frequency. The maximum pixel rate that a given MCLK frequency can support depends on the following: 1) 2) Pixel depth (number of bytes per pixel): 1 byte for 8 bpp, 2 bytes for 16 bpp, 3 bytes for 24 bpp. Number of additional bytes accessed for STN-DD frame buffering, usually one byte per pixel (independent of pixel depth in main display memory). This effect is discussed further in the next section. It applies only to STN-DD panels, not to CRT or TFT displays. Utilization efficiency. The percentage of peak memory bandwidth needed for RAS overhead (RASCAS cycles rather than CAS-only cycles), DRAM refresh, and CPU access. Peak memory bandwidth is the product of MCLK and the number of bytes accessed per MCLK (e.g., 664MB/sec for 83MHz MCLK). The graphics controller needs at least 20% of this peak bandwidth for RAS overhead (higher for STN-DD buffer accesses and CPU accesses due to shorter DRAM bursts). Allow at least an additional 10% bandwidth buffer for CPU accesses and DRAM refresh. This leaves 70% of MCLK cycles available for display refresh (10% allowance for the CPU may be grossly inadequate for demanding applications such as software MPEG playback). Multimedia frame capture. This factor is not included in the example calculations. Except where otherwise noted, the graphics controller mode support estimates do not include provision for frame capture from the video input port.
3)
4)
As an example, suppose MCLK is 83 MHz and the pixel depth is 16 bpp. Then the maximum supportable pixel rate for CRT and TFT displays is 83 MHz x 70% x 8 / 2 = 232.4 MHz (8 bytes per MCLK, 2 bytes per pixel). Any video mode that uses a 232.4 MHz or lower DCLK can be supported by the 83 MHz MCLK. For an STN-DD panel, the maximum supportable pixel rate in 16 bpp modes is 83 MHz x 70% x 8 / 3 = 154 MHz (8 bytes per MCLK, 3 bytes accessed per pixel). 16 bpp video modes using a 75 MHz or lower DCLK can be supported by the 83 MHz MCLK with an STN-DD panel.
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Clock Generation
STN-DD Panel Buffering
STN-DD panels require the upper and lower halves of the panel to be refreshed simultaneously. In addition, Temporal Modulated Energy Distribution (TMED) or Frame Rate Control (FRC) is needed to achieve more than 8 colors, since the panel itself supports only 3 bits per pixel (one bit each for red, green, and blue). The 69030 graphics accelerator implements STN-DD support using either a full frame buffer or a half frame buffer (programmable option). The buffer holds three bits per pixel, packed in groups of 10 pixels per DWORD. Thus, the buffer requires 0.4 bytes per pixel in addition to the main display memory. The half frame buffer operates as follows. As each pixel is read out of display memory, the appropriate 3bit code for the panel is calculated and sent to the panel. In addition, the proper 3-bit code for the same pixel in the NEXT frame is also calculated, with allowance for frame rate control. The second 3-bit code is written into the half frame buffer. During this same pixel time, the previously stored 3-bit code is read out of the half frame buffer and sent to the other half of the panel. The full frame buffer operates in a similar manner. As each two pixels are read out of display memory, the appropriate 3-bit codes for the panel are calculated and stored in the buffer. During the same two pixel times, previously stored 3-bit codes are read out of the buffer and sent to upper and lower halves of the panel. There is no difference between a half frame buffer and a full frame buffer in the effect on display memory bandwidth. Both options require 0.4 bytes per pixel to be read and written during each pixel time. If the buffer is located in main display memory, the total effect is 0.8 extra bytes of memory access per pixel (regardless of pixel depth). In 16 bpp modes, a total of 2.8 bytes of memory access must be performed per pixel - 2 bytes for the 16 original pixel bits, plus 0.8 byte for the buffer bits. The graphics controller actually reads and writes one DWORD in the buffer for every 10 pixels, which is the same as 0.8 bytes per pixel. For mode support calculations, it is usually best to assume 1.0 byte per pixel instead of 0.8, since the RAS overhead for STN-DD buffer accesses is somewhat higher than for normal pixel accesses due to shorter DRAM bursts. The half frame buffer has a timing characteristic for the panel that may be either a problem or an advantage, depending on the application. The panel is refreshed at twice the pixel rate imposed on the display memory. In simultaneous CRT and panel mode, this means that the pixel rate is dictated by the CRT requirements, and the panel is refreshed at twice that rate. This may exceed panel timing limitations. However, in panelonly mode, the pixel rate from display memory can be reduced to half of what a CRT would need, which imposes half the burden on display memory bandwidth and allows more complex video modes to be supported by the available display memory bandwidth. The full frame buffer allows the panel refresh rate to be the same as the CRT in simultaneous display mode, but requires the buffer size to be twice as large (full frame instead of half frame, though only 0.4 bytes per pixel).
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B-9
Horizontal and Vertical Clocking
Clocking within a horizontal scan line is generally programmed in units of 8 DCLK cycles (8 pixels), often referred to as "character" clocks (for graphics modes as well as text modes). The "character" clocks are numbered from 0 to n-1, where "n" is the total number of character clocks per horizontal scan (including blanking and border intervals as well as the "addressable video" interval). Character clock #0 corresponds to the start of the "addressable video" interval, also known as the "Display Enable" interval. Starting at character clock #0, the following horizontal timing events occur: * * * * * * End of Display Enable Start of horizontal blanking (end of right border) Horizontal sync pulse start and end End of horizontal blanking Start of left border (This border area is actually for the next physical scan line.) End of left border area and start of Display Enable (This corresponds to the "Horizontal Total" parameter.)
Similarly, vertical clocking is generally programmed in units of scan lines, numbered from 0 to m-1, where "m" is the total number of scan lines per complete frame and "0" corresponds to the first scan line containing addressable video information. Starting at scan line #0, the following vertical timing events occur: * * * * * End of addressable video Start of vertical blanking (end of bottom border) Vertical sync pulse start and end End of vertical blanking (start of top border) (This border area is actually for the next physical frame.) End of top border area and start of addressable video. This corresponds to the "Vertical Total" parameter.
Vertical timing can also be "interlaced," meaning that even numbered scan lines are displayed during one vertical sweep and odd numbered lines are displayed during the next vertical sweep. This allows more time (two vertical sweeps instead of one) to display a complete frame, which reduces video bandwidth requirements while preserving a reasonably flicker-free image. North American television standards use a 60 Hz vertical sync frequency, interlaced for a 30 Hz effective frame rate, with 525 scan lines total per frame (even lines plus odd, including blanking). The horizontal sync frequency is 525 x 30 Hz = 15.75 KHz. To achieve interlacing, the sweep of odd-numbered lines is offset by half of a scan line relative to the sweep of even-numbered lines. The vertical sync pulse for alternate frames occurs in the middle of a scan line interval (during vertical blanking) instead of at the end. North American television standards sweep 262.5 scan lines on each vertical sweep (60Hz). Each scan line remains full length, but the vertical sync for alternating frames occurs at the middle of the scan line. In this graphics controller, various extension registers allow the exact placement of the half-line vertical sync pulse to be programmable, for optimum centering of odd scan lines between adjacent even scan lines. Computer CRT displays generally need about 25% of the horizontal total for horizontal border and blanking intervals, and at least 5% of the vertical total for vertical border and blanking. Flat panels typically can operate with smaller margins for these "non-addressable" intervals.
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Panel Power Sequencing
C-1
Appendix C Panel Power Sequencing
Introduction
Flat panel displays are extremely sensitive to conditions where full biasing voltage VEE is applied to the liquid crystal material without enabling the control and data signals to the panel. This results in severe damage to the panel and may disable the panel permanently. The graphics controller provides a simple method to provide or remove power to the flat panel display in a sequence of stages when entering various modes of operation to conserve power and provide safe operation to the flat panel. Three pins called ENAVEE, ENAVDD and ENABKL are provided to regulate the LCD Bias Voltage (VEE), the driver electronics logic voltage (VDD), and the backlight voltage (BKL) to provide intelligent power sequencing to the panel. The delay between each stage in the sequence is programmable via the Panel Power Sequencing Delay Register (FR04). The graphics controller performs the `panel off' sequence when the STNDBY# input becomes low, or if bit 3 of the Power Down Control 1 Register (FR05) is set to 1. Conversely, the graphics controller performs the `panel on' sequence when the STNDBY# input becomes high, or if bit 3 of the Power Down Control 1 Register (FR05) is set to 0.
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Panel Power Sequencing
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Hardware Cursor and Pop Up Window
D-1
Appendix D Hardware Cursor and Pop Up Window
Introduction
This graphics controller provides a pair of hardware-based cursors, called "cursor 1" and "cursor 2". Cursor 1 is normally used to provide the arrow pointer in most GUI applications and operating systems. Cursor 2 has no pre-assigned purpose, however it is assumed that it will be usually used to provide some form of pop-up window. Off-screen memory in the frame buffer is used to provide the locations where the data for both cursor 1 and cursor 2 are kept. This allows each cursor to be displayed and used without altering the main display image stored in the frame buffer. Each cursor may have multiple patterns stored in these off-screen memory locations, making it possible to change each cursor's appearance simply by switching from one stored image to another. Two sets of eight registers (XRA0-XRA7 for cursor 1 and XRA8-XRAF for cursor 2) provide the means to configure and position both cursors. In each set of eight registers, two are used to enable, disable, and configure each cursor. Another pair of registers from each set specifies the base address within the frame buffer memory where the cursor data is kept. These registers also provide a way to select one of up to sixteen cursor patterns to be used. The remaining four registers of each set are used to provide the X and Y coordinates to control the current location of each cursor relative to the upper left-hand corner of the display. Two sets of four alternate color data positions added to the RAMDAC provide places in which the colors for each of the two cursors are specified (positions 0-3 for cursor 2 colors 0-3, and positions 4-7 for cursor 1 colors 0-3). These alternate color data positions are accessed by the same sub-addressing scheme used to access the standard color data positions of the main RAMDAC palette, with the exception that a bit in Pixel Pipeline Configuration Register 0 (XR80) must be set so that the alternate color data positions are accessible in place of the standard color data positions.
Basic Cursor Configuration
Cursor 1 and cursor 2 can each be independently disabled or configured for one of six possible modes using the Cursor 1 Control Register (XRA0) and the Cursor 2 Control Register (XRA8). Detailed descriptions of each of these six modes are provided later in this section. Horizontal and/or vertical stretching are functions that may be independently enabled or disabled for each cursor using these registers. Similar to the stretching functions used with the main display image, the stretching functions for each of the cursors only apply to flat panel displays. When enabled, the horizontal and vertical stretching functions for each cursor use the same stretching algorithms and parameter settings selected in the registers used to control the horizontal and vertical stretching functions for the main display image. The horizontal and vertical stretching functions for each cursor can be enabled or disabled entirely independently of the horizontal and vertical stretching functions for the main display image. These same two registers also provide the means to enable or disable blinking for each cursor, and to choose between two possible locations on the screen for the origin of the coordinate system used to specify the cursor location. A bit in each of these registers provides the ability to choose either the upper left-hand corner of the active display area, or the outer-most upper left-hand corner of the display border surrounding the active display area as the exact location of the origin for the coordinate system for each cursor. Finally, each of these registers allows the vertical extension function to be enabled or disabled for each cursor. The vertical extension function allows the height of the cursor to be specified independently from its width, allowing cursors that are not square in shape to be created. This function is discussed in more detail later in this section.
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Hardware Cursor and Pop Up Window
Base Address for Cursor Data
The Cursor 1 Base Address Low Register (XRA2) and the Cursor 1 Base Address High Register (XRA3) are used to program the base address in the frame buffer at which the cursor data for cursor 1 begins. The Cursor 2 Base Address Low Register (XRAA) and the Cursor 2 Base Address High Register (XRAB) provide this same function for cursor 2. The base address values stored in these registers actually specify an offset relative to the base address at which the frame buffer begins. The amount of space allocated for cursor data for each cursor is 4KB. More than one cursor pattern may be stored within this space, depending on the cursor size. While the bits in both the high and low base address registers for each of the cursors are combined to provide the base addresses, the upper four bits of each of the low base address registers (XRA2 for cursor 1 and XRAA for cursor 2) are used to select which of the available patterns stored within each space is to be used for each of the cursors. In the 32x32x2bpp AND/XOR pixel plane mode, up to sixteen 256 byte patterns can be stored in the 4KB memory space, and all four of the upper bits of the low base address registers are used to select one of these sixteen possible patterns. In all three modes with a cursor resolution of 64x64 pixels, up to four patterns of 1KB in size can be stored in the 4KB memory space, and the uppermost two of these four bits are used to select one of these four possible patterns (the other two bits should be set to 0). In both modes with a cursor resolution of 128x128 pixels, only up to two patterns of 2KB in size can be stored, and only the uppermost bit of the four bits is used to select between them (the other three bits should be set to 0).
Cursor Vertical Extension
The cursor vertical extension feature allows the vertical size (height) of either cursor in any of the six possible modes to be altered from the height normally dictated by the choice of cursor mode. The cursor mode still determines the width of the cursor. This feature allows the cursor to have a non-square shape. This feature is enabled via bit 3 of either the Cursor 1 Control Register (XRA0) for cursor 1 or the Cursor 2 Control Register (XRA8) for cursor 2. Once enabled, the height of the given cursor must be specified -either in the Cursor 1 Vertical Extension Register (XRA1) for cursor 1 or in the Cursor 2 Vertical Extension Register (XRA9) for cursor 2. Total size of the cursor data for a given cursor can not exceed the 4KB allotted for the cursor data of each cursor. This places a limit on the height of a cursor of given width and color depth. This also has implications concerning how many patterns may be stored in this space for the given cursor, and the mechanics of selecting which of those patterns is to be displayed using the upper four bits of the low base address register for each cursor.
Cursor Colors
The colors for drawing each of the two cursors are specified in two sets of four alternate color data positions added to the RAMDAC (positions 0-3 for cursor 2 colors 0-3, and positions 4-7 for cursor 1 colors 0-3). These alternate color data positions are accessed using the same sub-addressing scheme used to access the standard color data positions of the main RAMDAC palette, but with bit 0 in the Pixel Pipeline Configuration Register 0 (XR80) set so that the alternate color data positions are made accessible in place of the standard positions. If the use of a border is enabled, color data positions 6 and 7, which provide colors 2 and 3 for cursor 1, will be taken over to specify the border colors for the CRT and flat-panel. This will limit cursor 1 to only colors 0 and 1. This limit on cursor 1 will not impact either of the AND/XOR pixel plane modes, or either of the cursor modes with a cursor resolution of 128x128 pixels because none of these four modes use cursor colors 2 or 3.
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Cursor Positioning
Registers XRA4-XRA7 and registers XRAC-XRAF are used to position cursor 1 and cursor 2, respectively, on the display. Two registers from each group provide the high and low bytes for the value specifying the horizontal position and the other two provide the high and low bytes for the value specifying the vertical position. A bit in one of the configuration registers (XRA0 for cursor 1 and XRA8 for cursor 2) selects whether the values programmed into these registers are interpreted as being relative to the upper left-hand corner of the active display area or to the outer-most upper left-hand corner of the border surrounding the active display area. The values provided to these registers are signed 12-bit integers. Since the origin of the coordinate system is generally relative to the upper left corner of the display, a cursor appearing entirely within the active display area will have a positive horizontal position value and a negative vertical position value. These registers are double-buffered and synchronized to VSYNC to ensure that the cursor never appears to come apart in multiple fragments as it is being moved across the screen. To change a cursor position, all four of its position registers must be written, and they must be written in sequence (that is, in order from XRA4 to XRA7 for cursor 1 and in order from XRAC to XRAF for cursor 2.) The hardware will only update the position with the next VSYNC if the registers are written in sequence.
Cursor Modes
Each cursor can be independently disabled or set to one of six possible modes. This is done by using bits 2-0 in XRA0 for cursor 1 and in XRA8 for cursor 2. The main features which distinguish these modes from each other are the manner in which the cursor data is organized in memory and the meaning of the bits corresponding to each pixel position. The six possible modes are: 32x32x2bpp AND/XOR pixel plane mode 64x64x2bpp AND/XOR pixel plane mode 64x64x2bpp 4-color mode 64x64x2bpp 3-color and transparency mode 128x128x1bpp 2-color mode 128x128x1bpp 1-color and transparency mode The first two modes are designed to follow the Microsoft Windows 2-plane cursor data structure to ease the work of programming the cursor(s) for that particular GUI environment. The other four modes are intended to improve upon the first two modes by providing additional color options or a larger resolution. The following pages discuss the various modes in greater detail.
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Hardware Cursor and Pop Up Window
32x32x2bpp & 64x64x2bpp AND/XOR Pixel Plane Modes
These two modes are designed to follow the Microsoft Windows cursor data plane structure, which provides two colors that may be used to draw the cursor, a third color for transparency (which allows the main display image behind the cursor to show through) and a fourth color for inverted transparency (which allows the main display image behind the cursor to show through, but with its color inverted). Each pixel position within the cursor is defined by the combination of two bits of data, each of which is stored in planes referred to as the "AND" plane and the "XOR" plane. In the 32x32x2bpp AND/XOR pixel plane mode, it is possible to have up to 16 different 256byte patterns stored in a 4KB memory space starting at the base address specified in the low and high base address registers for the given cursor. In 64x64x2bpp AND/XOR pixel plane mode, only up to 4 different 1KB patterns may be stored. The following tables show how the cursor data is organized in memory for each of these two modes: Table D-1: Memory Organization 32x32x2bpp AND/XOR Pixel Plane Mode
Offset 000h 004h 008h 00Ch 010h 014h ... 0F0h 0F4h 0F8h 0FCh 100h 104h ... FF8h FFCh Plane AND AND XOR XOR AND AND ... AND AND XOR XOR AND AND ... XOR XOR Pixels 31-0 on line 0 of pattern 0 31-0 on line 1 of pattern 0 31-0 on line 0 of pattern 0 31-0 on line 1 of pattern 0 31-0 on line 2 of pattern 0 31-0 on line 3 of pattern 0 ... 31-0 on line 30 of pattern 0 31-0 on line 31 of pattern 0 31-0 on line 30 of pattern 0 31-0 on line 31 of pattern 0 31-0 on line 0 of pattern 1 31-0 on line 1 of pattern 1 ... 31-0 of line 30 of pattern 1 31-0 of line 31 of pattern 1
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Hardware Cursor and Pop Up Window Table D-2: Memory Organization 64x64x2bpp AND/XOR Pixel Plane Mode
Offset 000h 004h 008h 00Ch 010h 014h ... 3F0h 3F4h 3F8h 3FCh 400h 404h ... FF8h FFCh Plane AND AND XOR XOR AND AND ... AND AND XOR XOR AND AND ... XOR XOR Pixels 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 31-0 on line 1 of pattern 0 63-32 on line 1 of pattern 0 ... 31-0 on line 63 of pattern 0 63-32 on line 63 of pattern 0 31-0 on line 63 of pattern 0 63-32 on line 63 of pattern 0 31-0 on line 0 of pattern 1 63-32 on line 0 of pattern 1 ... 31-0 on line 63 of pattern 3 63-32 on line 63 of pattern 3
D-5
The meaning of the single bit in a given pixel position in the XOR plane changes depending on the bit in the corresponding position in the AND plane. If the value of the bit for a given pixel position in the AND plane is 0, then part of the cursor will be displayed at that pixel position and the value of the corresponding bit in the XOR plane selects one of the two available cursor colors to be displayed there. Otherwise if the value of the bit in the AND plane is 1, then that pixel position of the cursor will become transparent, allowing a pixel of the main display image behind the cursor to show through and the value of the corresponding bit in the XOR plane chooses whether or not the color of the pixel of the main display image will be inverted. Table D-3 summarizes this. Table D-3: Pixel Data 32x32x2bpp and 64x64x2bpp AND/XOR Pixel Plane Modes
AND Plane Pixel Data 0 0 1 1 XOR Plane Pixel Data 0 1 0 1 Color Displayed at the Corresponding Pixel Position Cursor color 0 Cursor color 1 Transparent. The pixel of the main display image behind cursor shows through Transparent, but inverted. The pixel of the main display image behind cursor shows through with inverted color
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64x64x2bpp 4-Color Mode
This mode provides four colors for drawing the cursor. There is no provision for transparency in the 64x64 pixel space occupied by the cursor so unless the image behind the cursor happens to be the same color as one of the four colors used to draw the cursor, the cursor will appear to be a 64 x 64 pixel square. Each pixel position within the cursor is defined by the combination of two bits, each of which is stored in planes referred to as plane 0 and plane 1. In this mode, it is possible to have up to 4 different 1KB patterns stored in a 4KB memory space starting at the base address specified in the low and high base address registers for the given cursor. The following tables show how the cursor data is organized in memory and the meaning of the two bits for each pixel position. Table D-4: Memory Organization 64x64x2bpp 4-Color Mode
Offset 000h 004h 008h 00Ch 010h 014h ... 3F0h 3F4h 3F8h 3FCh 400h 404h ... FF8h FFCh Plane 0 0 1 1 0 0 ... 0 0 1 1 0 0 ... 1 1 Pixels 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 31-0 on line 1 of pattern 0 63-32 on line 1 of pattern 0 ... 31-0 on line 63 of pattern 0 63-32 on line 63 of pattern 0 31-0 on line 63 of pattern 0 63-32 on line 63 of pattern 0 31-0 on line 0 of pattern 1 63-32 on line 0 of pattern 1 ... 31-0 on line 63 of pattern 3 63-32 on line 63 of pattern 3
Table D-5:
Pixel Data 64x64x2bpp 4-Color Mode
Plane 0 Pixel Data 0 0 1 1 Plane 1 Pixel Data 0 1 0 1 Color Displayed at the Corresponding Pixel Position Cursor color 0 Cursor color 1 Cursor color 2 Cursor color 3
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64x64x2bpp 3-Color and Transparency Mode
This mode provides three colors for drawing the cursor and a fourth color for transparency (which allows the main display image behind the cursor to show through). Each pixel position in the cursor is defined by the combination of two bits, stored in planes referred to as plane 0 and plane 1. In this mode, it is possible to have up to 4 1KB different patterns stored in a 4KB memory space starting at the base address specified in the low and high base address registers for the given cursor. The following tables show how the cursor data is organized in memory and the meaning of the two bits for each pixel position. Table D-6: Memory Organization 64x64x2bpp 3-Color & Transparency Mode
Offset 000h 004h 008h 00Ch 010h 014h ... 3F0h 3F4h 3F8h 3FCh 400h 404h ... FF8h FFCh Plane 0 0 1 1 0 0 ... 0 0 1 1 0 0 ... 1 1 Pixels 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 31-0 on line 1 of pattern 0 63-32 on line 1 of pattern 0 ... 31-0 on line 63 of pattern 0 63-32 on line 63 of pattern 0 31-0 on line 63 of pattern 0 63-32 on line 63 of pattern 0 31-0 on line 0 of pattern 1 63-32 on line 0 of pattern 1 ... 31-0 on line 63 of pattern 3 63-32 on line 63 of pattern 3
Table D-7:
Pixel Data 64x64x2bpp 3-Color & Transparency Mode
Plane 0 Pixel Data 0 0 1 1 Plane 1 Pixel Data 0 1 0 1 Color Displayed at the Corresponding Pixel Position Cursor color 0 Cursor color 1 Transparent Pixel of the image behind the cursor shows through Cursor color 3
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128x128x1bpp 2-Color Mode
This mode provides two colors for drawing the cursor. There is no provision for transparency in the 128x128 pixel space occupied by the cursor so unless the image behind the cursor happens to be the same color as one of the two colors used to draw the cursor, the cursor will appear as a 128x128 pixel square. In this mode, it is possible to have only up to 2 different 2KB patterns stored in a 4KB memory space starting at the base address specified in the low and high base address registers for the given cursor. The following tables show how the cursor data is organized in memory and the meaning of the bit for each position. Table D-8: Memory Organization 128x128x1bpp 2-Color Mode
Offset 000h 004h 008h 00Ch 010h 014h ... 7F0h 7F4h 7F8h 7FCh 800h 804h ... FF8h FFCh Pixels 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 95-64 on line 0 of pattern 0 127-96 on line 0 of pattern 0 31-0 on line 1 of pattern 0 63-32 on line 1 of pattern 0 ... 31-0 on line 127 of pattern 0 63-32 on line 127 of pattern 0 95-64 on line 127 of pattern 0 127-96 on line 127 of pattern 0 31-0 on line 0 of pattern 1 63-32 on line 0 of pattern 1 ... 95-64 on line 127 of pattern 1 127-96 on line 127 of pattern 1
Table D-9:
Pixel Data 128x128x1bpp 2-Color Mode
Pixel Data Bit 0 1 Color Displayed at the Corresponding Pixel Position Cursor color 2 Cursor color 3
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128x128x1bpp 1-Color and Transparency Mode
This mode provides one color for drawing the cursor and a second color for transparency (which allows the image behind the cursor to show through). In this mode, it is possible to have only up to 2 different 2KB patterns stored in a 4KB memory space starting at the base address specified in the low and high base address registers for the given cursor. The following tables show how the cursor data is organized in memory and the meaning of the bit for each position. Table D-10: Memory Organization 128x128x1bpp 1-Color & Transparency Mode
Offset 000h 004h 008h 00Ch 010h 014h ... 7F0h 7F4h 7F8h 7FCh 800h 804h ... FF8h FFCh Pixels 31-0 on line 0 of pattern 0 63-32 on line 0 of pattern 0 95-64 on line 0 of pattern 0 127-96 on line 0 of pattern 0 31-0 on line 1 of pattern 0 63-32 on line 1 of pattern 0 ... 31-0 on line 127 of pattern 0 63-32 on line 127 of pattern 0 95-64 on line 127 of pattern 0 127-96 on line 127 of pattern 0 31-0 on line 0 of pattern 1 63-32 on line 0 of pattern 1 ... 95-64 on line 127 of pattern 1 127-96 on line 127 of pattern 1
Table D-11:
Pixel Bit Definitions 128x128x1bpp 1-Color & Transparency Mode
Pixel Data Bit 0 1 Color Displayed at the Corresponding Pixel Position Transparent. Pixel of the image behind cursor shows through Cursor color 2
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BitBLT Operation
E-1
Appendix E BitBLT Operation
Introduction
The graphics controller provides a hardware-based BitBLT engine to offload the work of moving blocks of graphics data from the host CPU. Although the BitBLT engine is often used simply to copy a block of graphics data from the source to the destination, it also has the ability to perform more complex functions. The BitBLT engine is capable of receiving three different blocks of graphics data as input as shown in Figure E-1. The source data may exist either in the frame buffer or it may be provided by the host CPU from some other source such as system memory. The pattern data always represents an 8x8 block of pixels that must be located in the frame buffer, usually within the off-screen portion. The input destination data is the data already residing at the destination in the frame buffer prior to a BitBLT operation being performed. The output destination data is the data written to the destination as a result of a BitBLT operation. The BitBLT engine may be configured to use various combinations of the source, pattern, and input destination data as operands, in both bit-wise logical operations to generate the output destination data. It is intended that the BitBLT engine will perform these bit-wise and per-pixel operations on color graphics data that is at a color depth that matches the rest of the graphics system. However, if either the source or pattern data is monochrome, the BitBLT engine has the ability to put either block of graphics data through a process called "color expansion" which converts the monochrome graphics data to color. Since the destination is often a location in the on-screen portion of the frame buffer, it is assumed that any data already residing at the destination will be of the appropriate color depth.
Figure E-1: Block Diagram and Data Paths of the BitBLT Engine
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E-2
BitBLT Operation
Color Depth Configuration and Color Expansion
The graphics system can be configured for color depths of 1, 2, 4, 8, 16, 24, and 32 bits per pixel, while the BitBLT engine is intended to work only with graphics data having a color depth of only 8, 16, or 24 bits per pixel. It is assumed that the BitBLT engine will not be used when the graphics system has been configured for a color depth that the BitBLT engine was not designed to support. In theory, it is possible to configure the BitBLT engine and graphics system for different color depths, but this is not recommended. The configuration of the BitBLT engine for a given color depth dictates the number of bytes of graphics data that the BitBLT engine will read and write for each pixel while performing a BitBLT operation. It is assumed that any input destination data from the frame buffer will already be at the color depth to which the BitBLT engine is configured. Similarly, it is assumed that any source or pattern data used as an input will have this same color depth, unless one or both is monochrome. If either the source or pattern data is monochrome, the BitBLT engine will perform a process called "color expansion" to convert such monochrome data to color at the color depth to which the BitBLT engine has been set. During "color expansion" the individual bits of monochrome source or pattern data that correspond to individual pixels are converted to 8, 16, or 24 bits per pixel (i.e., 1, 2, or 3 bytes per pixel -- whichever is appropriate for the color depth to which the BitBLT engine has been set). If a given bit of monochrome source or pattern data carries a value of 1, then the byte(s) of color data resulting from the conversion process will be set to the value of a specified foreground color. If a given bit of monochrome source or The BitBLT engine is configured for a color depth of 8, 16, or 24 bits per pixel through either bits 5 and 4 of XR20, or bits 25 and 24 of BR04, depending upon the setting of bit 23 of BR04. Whether the source and pattern data are color or monochrome must be specified using bits 12 and 18, respectively, of BR04. The foreground and background colors for the color expansion of both monochrome source and pattern data may be specified using BR02 and BR01, respectively. Alternatively, if bit 27 of BR03 is set to 1, the foreground and background colors used in the color expansion of monochrome source data may be independently specified using BR0A and BR09, respectively.
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BitBLT Operation
E-3
Graphics Data Size Limitations
The BitBLT engine is capable of transferring very large quantities of graphics data. Any graphics data read from and written to the destination is permitted to represent a number of pixels that occupies up to 8191 scanlines and up to 8191 bytes per scanline at the destination. Therefore, the maximum number of pixels that may be represented per scanline's worth of graphics data depends on the color depth. Any source data must represent both the same number of pixels per scanline and the same number of scanlines as both the input and output destination data. Despite these constraints, if the source data is received from the host CPU via the BitBLT dataport, that source data may be received as part of a much larger block of data sent by the host CPU. The BitBLT engine may be programmed to skip over various quantities of bytes within such a block in order to reach the bytes containing valid source data. The actual number of scanlines and bytes per scan line required to accommodate both input and output destination data are set in BR08. These two values are essential in the programming of the BitBLT engine, because these values are used by the BitBLT engine to determine when a given BitBLT operation has been completed. It is important to note that writing a non-zero value to BR08 is the trigger that causes the BitBLT engine to begin a BitBLT operation. Therefore, all other registers must be set as desired for a given BitBLT operation before BR08.
Bit-Wise Operations
The BitBLT engine can perform any one of 256 possible bit-wise operations using various combinations of the source, pattern, and input destination data as inputs. These 256 possible bit-wise operations are designed to be compatible with the manner in which raster operations are specified in the BitBLT parameter block used in the Microsoft Windows environment, without translation. The choice of bit-wise operation selects which of the three inputs will be used, as well as the particular logical operation to be performed on corresponding bits from each of the selected inputs. The BitBLT engine will automatically forego reading any form of graphics data that has not been specified as an input by the choice of bit-wise operation. An 8-bit code written to BR04 chooses the bit-wise operation. The tables on the following pages list the available bit-wise operations and their corresponding 8-bit codes.
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E-4 Table E-1:
Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
BitBLT Operation Bit-Wise Operations and 8-bit Codes (00 - 5F)
Value Written to Bits at Destination writes all 0's not( D or ( P or S ))) D and ( not( P or S )) not( P or S ) S and ( not( D or P )) not( D or P ) not( P or ( not( D xor S ))) not( P or ( D and S )) S and ( D and ( notP )) not( P or ( D xor S )) D and ( notP ) not( P or ( S and ( notD ))) S and ( notP ) not( P or ( D and ( notS ))) not( P or ( not( D or S ))) notP P and ( not( D or S )) not( D or S ) not( S or ( not( D xor P ))) not( S or ( D and P )) not( D or ( not( P xor S ))) not( D or ( P and S )) P xor ( S xor (D and ( not( P and S )))) not( S xor (( S xor P ) and ( D xor S ))) ( S xor P ) and ( P xor D ) not( S xor ( D and ( not( P and S )))) P xor ( D or ( S and P )) not( S xor ( D and ( P xor S ))) P xor ( S or ( D and P )) not( D xor ( S and ( P xor D ))) P xor ( D or S ) not( P and ( D or S )) D and ( P and ( notS )) not( S or( D xor P )) D and ( notS ) not( S or ( P and ( notD ))) ( S xor P ) and ( D xor S ) not( P xor ( D and ( not( S and P )))) S xor ( D or ( P and S )) S xor ( D or ( not( P xor S ))) D and ( P xor S ) not( P xor ( S xor ( D or ( P and S )))) D and ( not( P and S )) not( S xor (( S xor P ) and ( P xor D ))) S xor ( P and ( D or S )) P xor ( S or ( notD )) P xor ( S or ( D xor P )) not( P and ( S or ( notD ))) Code 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F Value Written to Bits at Destination P and ( notS ) not( S or ( D and ( notP ))) S xor ( D or ( P or S )) notS S xor ( P or ( D and S )) S xor ( P or ( not( D xor S ))) S xor ( D or P ) not( S and ( D or P )) P xor ( S and ( D or P )) S xor ( P or ( notD )) S xor ( P or ( D xor S )) not( S and ( P or ( notD ))) P xor S S xor ( P or ( not( D or S ))) S xor ( P or ( D and ( notS ))) not( P and S ) P and ( S and ( notD )) not( D or ( P xor S )) ( S xor D ) and ( P xor D ) not( S xor ( P and ( not( D and S )))) S and ( notD ) not( D or ( P and ( notS ))) D xor ( S or ( P and D )) not( P xor ( S and ( D xor P ))) S and ( D xor P ) not( P xor ( D xor ( S or ( P and D )))) D xor ( P and ( S or D )) P xor ( D or ( notS )) S and ( not( D and P )) not( S xor (( S xor P ) or ( D xor S ))) P xor ( D or ( S xor P )) not( P and ( D or ( notS ))) P and ( notD ) not( D or ( S and ( notP ))) D xor (P or ( S and D )) not( S xor ( P and ( D xor S ))) not( D or ( not( P or S ))) notD D xor ( P or S ) not( D and ( P or S )) P xor ( D and ( S or P )) D xor ( P or ( notS )) D xor P D xor ( P or ( not( S or D ))) D xor ( P or ( S xor D )) not( D and ( P or ( notS ))) D xor ( P or ( S and ( notD ))) not( D and P )
Notes: S = Source Data P = Pattern Data D = Input Destination Data (data at destination prior to BitBLT operation)
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BitBLT Operation Table E-2:
Code 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
E-5
Bit-Wise Operations and 8-bit Codes (60 - BF)
Value Written to Bits at Destination P and ( D xor S ) not( D xor ( S xor ( P or ( D and S )))) D xor ( S and ( P or D )) S xor ( D or ( notP )) S xor ( D and ( P or S )) D xor ( S or ( notP )) D xor S S xor ( D or ( not( P or S ))) not( D xor ( S xor ( P or ( not( D or S ))))) not( P xor ( D xor S )) D xor ( P and S ) not( P xor ( S xor ( D and ( P or S )))) S xor ( D and P ) not( P xor ( D xor ( S and ( P or D )))) S xor ( D and ( P or ( notS ))) not( P and ( not( D xor S ))) P and ( not( D and S )) not( S xor (( S xor D ) and ( P xor D ))) S xor ( D or ( P xor S )) not( S and ( D or ( notP ))) D xor ( S or ( P xor D )) not( D and ( S or ( notP ))) S xor ( D or ( P and ( notS ))) not( D and S ) P xor ( D and S ) not( D xor ( S xor ( P and ( D or S )))) D xor ( P and ( S or ( notD ))) not( S and ( not( D xor P ))) S xor ( P and ( D or ( notS ))) not( D and ( not( P xor S ))) ( S xor P ) or ( D xor S ) not( D and ( P and S )) D and ( P and S ) not(( S xor P ) or ( D xor S )) D and ( not( P xor S )) not( S xor ( P and ( D or ( notS )))) S and ( not( D xor P )) not( P xor ( D and ( S or ( notP )))) D xor ( S xor ( P and ( D or S ))) not( P xor ( D and S )) D and S not( S xor ( D or ( P and ( notS )))) D and ( S or ( notP )) not( D xor ( S or ( P xor D ))) S and ( D or ( notP )) not( S xor ( D or ( P xor S ))) S xor (( S xor D ) and ( P xor D )) not( P and ( not( D and S ))) Code 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Value Written to Bits at Destination P and ( not( D xor S )) not( S xor ( D and ( P or ( notS )))) D xor ( P xor ( S and ( D or P ))) not( S xor ( P and D )) P xor ( S xor ( D and ( P or S ))) not( D xor ( P and S )) D xor ( P xor S ) P xor ( S xor ( D or ( not( P or S )))) not( S xor ( D or ( not( P or S )))) not( D xor S ) D xor ( P and ( notS )) not( S xor ( D and ( P or S ))) S xor ( P and ( notD )) not( D xor ( S and ( P or D ))) D xor ( S xor ( P or ( D and S ))) not( P and ( D xor S )) D and P not( P xor ( D or ( S and ( notP )))) D and ( P or ( notS )) not( D xor ( P or ( S xor D ))) not( P xor ( D or ( not( S or P )))) not( P xor D ) D xor ( S and ( notP )) not( P xor ( D and ( S or P ))) D and ( P or S ) not( D xor ( P or S )) D D or ( not( P or S)) S xor (P and ( D xor S )) not( D xor ( P or ( S and D ))) D or ( S and ( notP )) D or ( notP ) P and ( D or ( notS )) not( P xor ( D or ( S xor P ))) S xor (( S xor P ) or ( D xor S )) not( S and ( not( D and P ))) P xor ( S and ( notD )) not( D xor ( P and ( S or D ))) D xor ( P xor ( S or ( D and P ))) not( S and ( D xor P )) P xor ( S and ( D xor P )) not( D xor ( S or ( P and D ))) D or ( P and ( notS )) D or ( notS ) S xor ( P and ( not( D and S ))) not(( S xor D ) and ( P xor D )) D or ( P xor S ) D or ( not( P and S ))
Notes: S = Source Data P = Pattern Data D = Input Destination Data (data at destination prior to BitBLT operation)
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E-6 Table E-3:
Code C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
BitBLT Operation Bit-Wise Operations and 8-bit Codes (C0 - FF)
Value Written to Bits at Destination P and S not( S xor ( P or ( D and ( notS )))) not( S xor ( P or ( not( D or S )))) not( P xor S ) S and ( P or ( notD )) not( S xor ( P or ( D xor S ))) S xor ( D and ( notP )) not( P xor ( S and ( D or P ))) S and ( D or P ) not( S xor ( P or D )) D xor ( P and ( S xor D )) not( S xor ( P or ( D and S ))) S S or ( not( D or P )) S or ( D and ( notP )) S or ( notP ) P and ( S or ( notD )) not( P xor ( S or ( D xor P ))) P xor ( D and ( notS )) not( S xor ( P and ( D or S ))) S xor (( S xor P ) and ( P xor D )) not( D and ( not( P and S ))) P xor ( S xor ( D or ( P and S ))) not( D and ( P xor S )) P xor ( D and ( S xor P )) not( S xor ( D or ( P and S ))) D xor ( P and ( not( S and D ))) not(( S xor P ) and ( D xor S )) S or ( P and ( notD )) S or ( notD ) S or ( D xor P ) S or ( not( D and P )) Code E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Value Written to Bits at Destination P and ( D or S ) not( P xor ( D or S )) D xor ( S and ( P xor D )) not( P xor ( S or ( D and P ))) S xor ( D and ( P xor S )) not( P xor ( D or ( S and P ))) S xor ( D and ( not( P and S ))) not(( S xor P ) and ( P xor D )) S xor (( S xor P ) and ( D xor S )) not( D xor ( S xor ( P and ( not( D and S ))))) D or ( P and S ) D or ( not( P xor S )) S or ( D and P ) S or ( not( D xor P )) D or S S or ( D or ( notP )) P P or ( not( D or S )) P or ( D and ( notS )) P or ( notS ) P or ( S and ( notD )) P or ( notD ) P or ( D xor S ) P or ( not( D and S )) P or ( D and S ) P or ( not( D xor S )) D or P D or ( P or ( notS )) P or S P or ( S or ( notD )) D or ( P or S ) writes all 1's
Notes: S = Source Data P = Pattern Data D = Input Destination Data (data at destination prior to BitBLT operation)
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Per-Pixel Write Masking
The BitBLT engine is able to perform per-pixel write-masking with various data sources used as pixel masks to constrain which pixels at the destination will actually be written to by the BitBLT engine. As shown in the figure below, either monochrome source or monochrome pattern data may be used as a pixel mask, but not color source or color pattern. Another available pixel mask called "color transparency" is derived by comparing a particular color to either the color already specified for a given pixel at the destination or the color that results from the bit-wise operation performed for a given pixel.
Figure E-2: Block Diagram and Data Paths of the BitBLT Engine Bits 13 and 17 of BR04 are used to select either the monochrome source or the monochrome pattern data as a pixel mask. When this feature is used, the bits in either the monochrome source or the monochrome pattern data that carry a value of 0 cause the bytes of the corresponding pixel at the destination to not be written to by the BitBLT engine, thereby preserving whatever data already residing within those bytes. This feature can be used in writing characters to the display in a way that preserves the pre-existing backgrounds behind those characters. Bits 14 through 16 of BR04 are used to select and enable 1 of 4 forms of per-pixel write-masking, each using a different color comparison as a mask. Bit 14 is used to enable this function. Bit 15 chooses between two different comparisons of color values. Depending on the setting of bit 15, a comparison is made between a key color (carried by either BR01 or BR09) and either the color already specified in the bytes for each of the pixels at the destination or the color resulting from the bit-wise operation being performed for each pixel. Bit 16 chooses whether the overwriting of the bytes at the destination will occur when the two compared values are found to be equal or when they are found not to be equal.
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BitBLT Operation
When the Source and Destination Locations Overlap
When the source and destination locations are both within the frame buffer, it is possible to have BitBLT operations in which these locations overlap. This frequently occurs in BitBLT operations where a user is shifting the position of a graphical item on the display by only a few pixels. In these situations, the BitBLT engine must be programmed so that output destination data is not written to the part of the destination that overlaps the source before the source data in the area of overlap has been read. Otherwise, the source data will become corrupted as shown in the figure below.
Figure E-3: Source Corruption in BitBLT with Overlapping Source and Destination Locations
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The BitBLT engine reads from the source and writes to the destination starting with the left-most pixel in the top-most line of both, as shown in step (a). As shown in step (b), corruption of the source data has already started with the copying of the top-most line in step (a) -- part of the source that originally contained lightercolored pixels has now been overwritten with darker-colored pixels. More source data corruption occurs as steps (b) through (d) are performed. At step (e), another line of the source data is read, but the two rightmost pixels of this line are in the region where the source and destination locations overlap, and where the source has already been overwritten as a result of the copying of the top-most line in step (a). Starting in step (f), darker-colored pixels can be seen in the destination where lighter-colored pixels should be. This errant effect occurs repeatedly throughout the remaining steps in this BitBLT operation. As more lines are copied from the source to the destination, it becomes clear that the end result is not as originally intended. The BitBLT engine can be programmed to alter the order in which source data is read and destination data is written when necessary to avoid the kind of source data corruption problem illustrated earlier. Bits 8 and 9 of BR04 provide the ability to change the point at which the BitBLT engine begins reading and writing data from the upper left-hand corner (the usual starting point) to one of the other three corners. In other words, through the use of these two bits, the BitBLT engine may be set to read data from the source and write it to the destination starting at any of the four corners of the panel. The following figure shows how this feature can be used to perform the same BitBLT operation illustrated earlier, but without corrupting the source data.
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BitBLT Operation
Figure E-4: Correctly Performed BitBLT with Overlapping Source and Destination Locations The BitBLT engine reads the source data and writes the destination data starting with the right-most pixel of the bottom-most line. By doing this, no pixel existing where the source and destination locations overlap will ever be written to before it is read from by the BitBLT engine. By the time the BitBLT operation has reached step (e) where two pixels existing where the source and destination locations overlap are about to be overwritten, the source data for those two pixels has already been read.
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The figure below shows the recommended starting points to be used in each of the 8 possible ways in which the source and destination could overlap. In general, the starting point should be within the area in which the overlap occurs.
Figure E-5: Suggested Starting Points for Possible Source and Destination Overlap Situations
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BitBLT Operation
Contiguous vs. Discontiguous Graphics Data
Graphics data stored in memory, particularly in the frame buffer of a graphics system, has organizational characteristics that often distinguish it from other varieties of data. The main distinctive feature is the tendency for graphics data to be organized in multiple sub-blocks of bytes, instead of a single contiguous block of bytes. Figure E-6 shows an example of contiguous graphics data -- a horizontal line made up of six adjacent pixels within a single scanline on a display with a resolution of 640x480. If it is presumed that the graphics system has been set to 8 bits per pixel, and that the first byte of frame buffer memory at offset 0h corresponds to the upper left-most pixel of this display, then the six pixels that make this horizontal line starting at coordinates (256, 256) would occupy six bytes starting at frame buffer offset 28100h, and ending at offset 28105h. In this case, this horizontal line exists entirely within one scanline on the display, and so the graphics data for all six of these pixels exists within a single contiguous block comprised of these six bytes. In this simple case, the starting offset and the number of bytes are the only pieces of information that a BitBLT engine would require to read this block of data.
Figure E-6: On-Screen Single 6-Pixel Line in the Frame Buffer The simplicity of the preceding example of a single horizontal line contrasts sharply to the example of discontiguous graphics data depicted in Figure E-7. The simple six-pixel line of Figure E-6 is now accompanied by three more six-pixel lines placed on subsequent scan lines, resulting in the 6x4 block of pixels shown. Since there are other pixels on each of the scan lines on which this 6x4 block exists that are not part of this 6x4 block, what appears to be a single 6x4 block of pixels on the display must be represented by a discontiguous block of graphics data made up of 4 separate sub-blocks of six bytes apiece in the frame buffer at addresses 28100h, 28380h, 28600h, and 28880h. This situation makes the task of reading what appears to be a simple 6x4 block of pixels more complex. Two characteristics of this 6x4 block of pixels help simplify the task of specifying the locations of all 24 bytes of this discontiguous block of graphics data. First, all four of the sub-blocks are of the same length. Second, the four sub-blocks are separated from each other at equal intervals. The BitBLT engine was designed to make use of these characteristics of graphics data to simplify the programming required to handle discontiguous blocks of graphics data. For such a situation, the BitBLT
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engine requires only four pieces of information: the starting address of the first sub-block, the length of a sub-block, the offset (in bytes) of the starting address of each subsequent sub-block, and the quantity of sub-blocks.
Figure E-7: On-Screen 6x4 Array of Pixels in the Frame Buffer
Source Data
The source data may either exist in the frame buffer where the BitBLT engine may read it directly, or it may be provided to the BitBLT engine by the host CPU. The block of source graphics data may be either contiguous or discontiguous, and may be either in color (with a color depth that matches that to which the BitBLT engine has been set) or monochrome. Bit 10 of the BitBLT Control Register (BR04) specifies whether the source data exists in the frame buffer or is provided by the CPU. Having the source data in the frame buffer will result in increased performance since the BitBLT engine will be able to access it directly without involving the host CPU. If the source data resides within the frame buffer, then the Source Address Register (BR06) is used to specify the address of the source data as an offset from the beginning of the frame buffer at which the block of source data begins. However, if the host CPU provides the source data, then this register takes on a different function and the three least-significant bits of the Source Address Register (BR06) can be used to specify a number of bytes that must be skipped in the first quadword received from the host CPU to reach the first byte of valid source data. In cases where the host CPU provides the source data, it does so by writing the source data to the BitBLT data port, a 64KB memory space on the host bus. There is no actual memory allocated to this memory space, so any data that is written to this location cannot be read back. This memory space is simply a range of memory addresses that the BitBLT engine's address decoder watches for the occurrence of any memory writes. The BitBLT engine loads all data written to any memory address within this memory space in the order in which it is written, regardless of the specific memory address to which it is written and uses that data as the source data in the current BitBLT operation. The block of bytes sent by the host CPU to this data port must be quadword-aligned, although the source data contained within the block of bytes does not need to be aligned. As mentioned earlier, the least significant three bits of the Source Address Register (BR06) are used to specify the number of bytes that must be skipped in the first quadword to reach the first byte of valid source data.
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BitBLT Operation
To accommodate discontiguous source data, the Source and Destination Offset Register (BR00) can be used to specify the offset in bytes from the beginning of one scan line's worth source data to the next. Otherwise, if the source data is contiguous, then an offset equal to the length of a scan line's worth of source data should be specified.
Monochrome Source Data
Bit 12 of the BitBLT Control Register (BR04) specifies whether the source data is color or monochrome. Since monochrome graphics data only uses one bit per pixel, each byte of monochrome source data typically carries data for 8 pixels which hinders the use of byte-oriented parameters when specifying the location and size of valid source data. Some additional parameters must be specified to ensure the proper reading and use of monochrome source data by the BitBLT engine. The BitBLT engine also provides additional options for the manipulation of monochrome source data versus color source data. The various bit-wise logical operations and per-pixel write-masking operations were designed to work with color data. In order to use monochrome data, the BitBLT engine converts it into color through a process called color expansion, which takes place as a BitBLT operation is performed. In color expansion, the single bits of monochrome source data are converted into one, two, or three bytes (depending on the color depth to which the BitBLT engine has been set) of color data that are set to carry value corresponding to either the foreground or background color that have been specified for use in this conversion process. If a given bit of monochrome source data carries a value of 1, then the byte(s) of color data resulting from the conversion process will be set to carry the value of the foreground color. If a given bit of monochrome source data carries a value of 0, then the resulting byte(s) will be set to the value of the background color. The foreground and background colors used in the color expansion of monochrome source data can be set in the Pattern/Source Expansion Foreground Color Register (BR02) and the Pattern/Source Expansion Background Color Register (BR01), in which case these colors will be the same colors as those used in the color expansion of monochrome pattern data. However, it is also possible to set the colors for the color expansion of monochrome source data independently of those set for the color expansion of monochrome pattern data by using the Source Expansion Foreground Color Register (BR0A) and the Source Expansion Background Color Register (BR09). Bit 27 in the BitBLT Monochrome Source Control Register (BR03) is used to select between one or the other of these two sets of registers. The BitBLT engine requires that the alignment of each scan line's worth of monochrome source data be specified. In other words, whether each scan line's worth of monochrome source data can be assumed to start on quadword, doubleword, word, or byte boundaries, or that it cannot be assumed to start on any such boundary must be specified using bits 26-24 of the Monochrome Source Control Register (BR03). The BitBLT engine also provides various clipping options for use with monochrome source data. Bits 21-16 of the Monochrome Source Control Register (BR03) allow the BitBLT engine to be programmed to skip up to 63 of the 64 bits in the first quadword of a block of monochrome source data to reach the first bit of valid source data. Depending on the width of the block of pixels represented by the monochrome source data, this option can also be used to implement a way of clipping the monochrome source data from the top. Bits 5-0 of this register allow up to 63 of the 64 bits in the first quadword in each scan line's worth of monochrome source data to be skipped to reach the first bit of valid source data in each scan line's worth. This option can be used to implement the clipping of each scan line's worth of monochrome source data from the left. Bits 13-8 of this register provides similar functionality for clipping monochrome source data from the right.
Pattern Data
The pattern data must exist within the frame buffer where the BitBLT engine may read it directly. The host CPU cannot provide the pattern data to the BitBLT engine. As shown in Figure E-8, the block of pattern graphics data always represents a block of 8x8 pixels. The bits or bytes of a block of pattern data may be organized in the frame buffer memory in only one of four ways, depending upon its color depth which may be 8, 16, or 24 bits per pixel (whichever matches the color depth to which the BitBLT engine has been set), or monochrome.
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Figure E-8: Pattern Data (Always an 8x8 Array of Pixels)
The Pattern Address Register (BR05) is used to specify the address of the pattern data as an offset from the beginning of the frame buffer at which the block of pattern data begins. The three least significant bits of the address written to this register are ignored, because the address must be in terms of quadwords. This is because the pattern must always be located on an address boundary equal to its size. Monochrome patterns take up 8 bytes, or a single quadword of space, and therefore, must be located on a quadword boundary. Similarly, color patterns with color depths of 8 and 16 bits per pixel must start on 64-byte and 128-byte boundaries, respectively. Color patterns with color depths of 24 bits per pixel must start on 256byte boundaries, despite the fact that the actual color data fills only 3 bytes per pixel. Figures E-9, E-10, E.3-11, and E-12 show how monochrome, 8bpp, 16bpp, and 24bpp pattern data is organized in memory.
Figure E-9: Monochrome Pattern Data -- Occupies a Single Quadword
Figure E-10: 8bpp Pattern Data -- Occupies 64 Bytes (8 Quadwords)
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BitBLT Operation
Figure E-11: 16bpp Pattern Data -- Occupies 128 Bytes (16 Quadwords)
Figure E-12: 24bpp Pattern Data -- Occupies 256 Bytes (32 Quadwords) As is shown in Figure E-12, there are four bytes allocated for each pixel on each scan line's worth of pattern data, which allows each scan line's worth of 24bpp pattern data to begin on a 32-byte boundary. The extra ("fourth") unused bytes of each pixel on a scan line's worth of pattern data are collected together in the last 8 bytes (the last quadword) of each scan line's worth of pattern data. Bit 18 of the BitBLT Control Register (BR04) specifies whether the pattern data is color or monochrome. The various bit-wise logical operations and per-pixel write-masking operations were designed to work with color data. In order to use monochrome pattern data, the BitBLT engine is designed to convert it into color through a process called "color expansion" which takes place as a BitBLT operation is performed. In color expansion, the single bits of monochrome pattern data are converted into one, two, or three bytes (depending on the color depth to which the BitBLT engine has been set) of color data that are set to carry values corresponding to either the foreground or background color that have been specified for use in this process. The foreground color is used for pixels corresponding to a bit of monochrome pattern data that carry the value of 1, while the background color is used where the corresponding bit of monochrome pattern data carries the value of 0. The foreground and background colors used in the color expansion of monochrome pattern data can be set in the Pattern/Source Expansion Foreground Color Register (BR02)
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and Pattern/Source Expansion Background Color Register (BR01). Depending upon the setting of bit 27 in the Monochrome Source Control Register (BR03), these same two registers may also specify the foreground and background colors to be used in the color expansion of the source data.
Destination Data
If the destination is within the frame buffer, then there are actually two different types of "destination data": the graphics data already residing at the location that is designated as the destination, and the data that is to be written into that very same location as a result of a BitBLT operation. If, however, the destination is selected so that the BitBLT engine is to provide its output to the host CPU, then the destination data provided to the host CPU is the only kind there is. Blocks of destination data to be read from and written to the destination may be either contiguous or discontiguous. All data written to the destination will have the color depth to which the BitBLT engine has been set. It is presumed that any data already existing at the destination which will be read by the BitBLT engine will also be of this same color depth -- the BitBLT engine neither reads nor writes monochrome destination data. Bit 11 of the BitBLT Control Register (BR04) is used to specify whether the destination data is to be written to a location within the frame buffer, or is to be provided to the host CPU. If the destination is within the frame buffer, the Destination Address Register (BR07) is used to specify the address of the destination as an offset from the beginning of the frame buffer at which the destination location begins. Otherwise, only bits 2-0 of the Destination Address Register (BR07) are used, and there purpose is to specify which byte in the first quadword of destination data provided to the host CPU is the first byte of actual destination data. To accommodate discontiguous destination data, the Source and Destination Offset Register (BR00) can be used to specify the offset in bytes from the beginning of one scan line's worth of destination data to the next. Otherwise, if the destination data is contiguous, then an offset equal to the length of a scan line's worth of destination data should be specified.
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BitBLT Operation
BitBLT Programming Examples Pattern Fill -- A Very Simple BitBLT
In this example, a rectangular area on the screen is to be filled with a color pattern stored as pattern data in off-screen memory. The screen has a resolution of 1024x768 and the graphics system has been set to a color depth of 8 bits per pixel. As shown in Figure E-13, the rectangular area to be filled has its upper left-hand corner at coordinates (128, 128) and its lower right-hand corner at coordinates (191, 191). These coordinates define a rectangle covering 64 scan lines, each scan line's worth of which is 64 pixels in length -- in other words, an array of 64x64 pixels. Presuming that the pixel at coordinates (0, 0) corresponds to the byte at address 00h in the frame buffer memory, the pixel at (128, 128) corresponds to the byte at address 20080h.
Figure E-13: On-Screen Destination for Example Pattern Fill BitBLT As shown in Figure E-14, the pattern data occupies 64 bytes starting at address 100000h. As always, the pattern data represents an 8x8 array of pixels. Before programming the BitBLT engine in any way, bit 0 of the BitBLT Configuration Register (XR20) or bit 31 of the BitBLT Control Register (BR04) should be checked to see if the BitBLT engine is currently busy. The BitBLT engine should not be programmed in any way until all BitBLT operations are complete and the BitBLT engine is idle. Once the BitBLT engine is idle, programming the BitBLT engine for the operation in this example should begin by making sure that the BitBLT Configuration Register (XR20) is set to 00h, in order to specify a color depth of 8 bits per pixel and enable normal operation. Alternatively, if bit 23 of the BitBLT Control Register (BR04) is set to 1, then the color depth of the BitBLT engine may be set to 8 bits per pixel by setting bits 25 and 24 of the same register to 0, although it is still necessary to ensure that at least bit 1 of the BitBLT Configuration Register is set to 0 to enable normal operation. The BitBLT Control Register (BR04) is used to select the features to be used in this BitBLT operation, and must be programmed carefully. Bits 22-20 should be set to 0 to select the top-most horizontal row of the pattern as the starting row used in drawing the pattern starting with the top-most scan line covered by the destination. Since actual pattern data will be used, bit 19 should be set to 0. The pattern data is in color with a color depth of 8 bits per pixel, so bits 18 and 17 should also be set to 0. Since this BitBLT operation
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does not use per-pixel write-masking, bits 16-13 should be set to 0. Bit 12 should be set to 0 to ensure that the settings in the Monochrome Source Control Register (BR03) will have no effect on this BitBLT operation. Bit 11 should be set to 0 to configure the BitBLT engine for a destination within the frame buffer. The setting of bits 10-8 do not affect this BitBLT operation, since source data is not used. Therefore, these bits might as well be set to zero as a default. Finally, bits 7-0 should be programmed with the 8-bit value of F0h to select the bit-wise logical operation in which a simple copy of the pattern data to the destination takes place. Selecting this bit-wise operation in which no source data is used as an input causes the BitBLT engine to automatically forego either reading source data from the frame buffer or waiting for the host CPU to provide it. Bits 28-16 of the Source and Destination Offset Register (BR00) must be programmed with number of bytes in the interval from the start of one scan line's worth of destination data to the next. Since the color depth is 8 bits per pixel and the horizontal resolution of the display is 1024, the value to be programmed into these bits is 400h, which is equal to the decimal value of 1024. Since this BitBLT operation does not use source data, the BitBLT engine ignores bits 12-0. Bits 22-3 of the Pattern Address Register (BR05) must be programmed with the address of the pattern data. This address is specified as an offset from the beginning of the frame buffer where the pattern data begins. In this case, the address is 100000h. Similarly, bits 22-0 of the Destination Address Register (BR07) must be programmed with the address of the destination, i.e., the offset from the beginning of the frame buffer of the byte at the destination that will be written to first. In this case, the address is 20080h, which corresponds to the byte representing the pixel at coordinates (128, 128).
Figure E-14: Pattern Data for Example Pattern Fill BitBLT This BitBLT operation does not use the values in the Pattern/Source Expansion Background Color Register (BR01), the Pattern/Source Expansion Foreground Color Register (BR02), the Monochrome Source Control Register (BR03), the Source Address Register (BR06), the Source Expansion Background Color Register (BR09), or the Source Expansion Foreground Color Register (BR0A). The Destination Width and Height Register (BR08) must be programmed with values that describe to the BitBLT engine the 64x64 pixel size of the destination location. Bits 28-16 should be set to carry the value of 40h, indicating that the destination location covers 64 scan lines. Bits 12-0 should be set to carry the value of 40h, indicating that each scan line's worth of destination data occupies 64 bytes. The act of writing a non-zero value for the height to the Destination Width and Height Register (BR08) is what signals the BitBLT engine to begin performing this BitBLT operation. Therefore, it is important that all other programming of the BitBLT registers be completed before this is done.
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BitBLT Operation
Figure E-15 shows the end result of performing this BitBLT operation. The 8x8 pattern has been repeatedly copied ("tiled") into the entire 64x64 area at the destination.
Figure E-15: Results of Example Pattern Fill BitBLT
Drawing Characters Using a Font Stored in System Memory
In this example BitBLT operation, a lowercase letter "f" is to be drawn in black on a display with a gray background. The resolution of the display is 1024x768, and the graphics system has been set to a color depth of 8 bits per pixel. Figure E-16 shows the display on which this letter "f" is to be drawn. As shown in this figure, the entire display is shaded gray. The letter "f" is to be drawn into an 8x8 region on the display with the upper left-hand corner at the coordinates (128, 128).
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Figure E-17 shows both the 8x8 pattern making up the letter "f" and how it is represented somewhere in the host's system memory -- the actual address in system memory is not important. The letter "f" is represented in system memory by a block of monochrome graphics data that occupies 8 bytes. Each byte carries the 8 bits needed to represent the 8 pixels in each scan line's worth of this graphics data. This type of pattern is often used to store character fonts in system memory.
Figure E-16: On-Screen Destination for Example Character Drawing BitBLT
Figure E-17: Source Data in System Memory for Example Character Drawing BitBLT During this BitBLT operation, the host CPU will read this representation of the letter "f" from system memory, and write it to the BitBLT engine by performing memory writes to the BitBLT data port. The BitBLT engine will receive this data from the host CPU and use it as the source data for this BitBLT operation. The BitBLT engine will be set to the same color depth as the graphics system ( 8 bits per pixel, in this case. Since the source data in this BitBLT operation is monochrome, color expansion must be used to convert it to an 8 bpp color depth. To ensure that the gray background behind this letter "f" is preserved, per-pixel write masking will be performed, using the monochrome source data as the pixel mask. As in the example of the pattern fill BitBLT operation, the first step before programming the BitBLT engine in any way is to check either bit 0 of the BitBLT Configuration Register (XR20) or bit 31 of the BitBLT Control Register (BR04) to see if the BitBLT engine is currently busy. After waiting until the BitBLT engine is idle,
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BitBLT Operation
programming the BitBLT engine should begin by making sure that the BitBLT Configuration Register (XR20) is set to 00h, to specify a color depth of 8 bits per pixel and to enable normal operation. Alternatively, if bit 23 of the BitBLT Control Register (BR04) is set to 1, then the color depth of the BitBLT engine may be set to 8 bits per pixel by setting bits 25 and 24 of the same register to 0, although it is still necessary to ensure that at least bit 1 of the BitBLT Configuration Register is set to 0 to enable normal operation. The BitBLT Control Register (BR04) is used to select the features to be used in this BitBLT operation. Since pattern data is not required for this operation, the BitBLT engine will ignore bits 22-17, however as a default, these bits can be set to 0. Since monochrome source data will be used as the pixel mask for the per-pixel write-masking operation used in this BitBLT operation, bits 16-14 must be set to 0, while bit 13 should be set to 1. Bit 12 should be set to 1, to specify that the data source is monochrome. Bit 11 should be set to 0 to configure the BitBLT engine for a destination within the frame buffer. Bit 10 should be set to 1, to indicate that the source data will be provided by the host CPU. Presuming that the host CPU will provide the source data starting with the byte that carries the left-most pixel on the top-most scan line's worth of the source data, bits 9 and 8 should both be set to 0. Finally, bits 7-0 should be programmed with the 8-bit value CCh to select the bit-wise logical operation that simply copies the source data to the destination. Selecting this bit-wise operation in which no pattern data is used as an input, causes the BitBLT engine to automatically forego reading pattern data from the frame buffer. Unlike the earlier example of a pattern fill BitBLT operation where the Monochrome Source Control Register (BR03) was entirely ignored, several features of this register will be used in this BitBLT operation. Bit 27 of this register will be set to 0, thereby selecting the Pattern/Source Expansion Foreground Color Register (BR02) to specify the color with which the letter "f" will be drawn. This example assumes that the source data will be sent in one quadword that will be quadword-aligned. Therefore, bits 26, 25, and 24, which specify alignment should be set to 1, 0, and 1, respectively. Since clipping will not be performed in this BitBLT operation, bits 21-16, 13-8, and 5-0 should all be set to 0. Bits 28-16 of the Source and Destination Offset Register (BR00) must be programmed with a value equal to number of bytes in the interval between the first bytes of each adjacent scan line's worth of destination data. Since the color depth is 8 bits per pixel and the horizontal resolution of the display is 1024 pixels, the value to be programmed into these bits is 400h, which is equal to the decimal value of 1024. Since the source data used in this BitBLT operation is monochrome, the BitBLT engine will not use a byte-oriented offset value for the source data. Therefore, bits 12-0 will be ignored. Since the source data is monochrome, color expansion is required to convert it to color with a color depth of 8 bits per pixel. Since the Pattern/Source Expansion Foreground Color Register (BR02) was selected to specify the foreground color of black to be used in drawing the letter "f", this register must be programmed with the value for that color. With the graphics system set for a color depth of 8 bits per pixel, the actual colors are specified in the RAMDAC palette, and the 8 bits stored in the frame buffer for each pixel actually specify the index used to select a color from that palette. This example assumes that the color specified at index 00h in the palette is black, and therefore bits 7-0 of this register should be set to 00h to select black as the foreground color. The BitBLT engine ignores bits 23-8 of this register because the selected color depth is 8 bits per pixel. Even though the color expansion being performed on the source data normally requires that both the foreground and background colors be specified, the value used to specify the background color is not important in this example. Per-pixel write-masking is being performed with the monochrome source data as the pixel mask, which means that none of the pixels in the source data that will be converted to the background color will ever be written to the destination. Since these pixels will never be seen, the value programmed into the Pattern/Source Expansion Background Color Register (BR01) to specify a background color is not important. Since the CPU is providing the source data, and this source data is monochrome, the BitBLT engine ignores all of bits 22-0 of the Source Address Register (BR06). Bits 22-0 of the Destination Address Register (BR07) must be programmed with the address of the destination data. This address is specified as an offset from the start of the frame buffer of the pixel at the destination that will be written to first. In this case, the address is 20080h, which corresponds to the byte representing the pixel at coordinates (128, 128).
efmp69030 Databook
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BitBLT Operation
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This BitBLT operation does not use the values in the Pattern Address Register (BR05), the Source Expansion Background Color Register (BR09), or the Source Expansion Foreground Color Register (BR0A). The Destination Width and Height Register (BR08) must be programmed with values that describe to the BitBLT engine the 8x8 pixel size of the destination location. Bits 28-16 should be set to carry the value of 8h, indicating that the destination location covers 8 scan lines. Bits 12-0 should be set to carry the value of 8h, indicating that each scan line's worth of destination data occupies 8 bytes. As mentioned in the previous example, the act of writing a non-zero value for the height to the Destination Width and Height Register (BR08) provides the BitBLT engine with the signal to begin performing this BitBLT operation. Therefore, it is important that all other programming of the BitBLT engine registers be completed before this is done. Figure E-18 shows the end result of performing this BitBLT operation. Only the pixels that form part of the actual letter "f" have been drawn into the 8x8 destination location on the display, leaving the other pixels within the destination with their original gray color.
Figure E-18: Results of Example Character Drawing BitBLT
efmp69030 Databook
Revision 1.3 11/24/99
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BitBLT Operation
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efmp69030 Databook
Revision 1.3 11/24/99
efmp 69030
Intel Corporation 350 East Plumeria Drive CHP3-102 PCG San Jose San Jose, CA 95134 Phone: 408-765-8080 FAX: 408-545-9812 www.intel.com Title: Publication No.: Stock No.: Revision No.: Date: 69030 Databook DB182.3 010-182-003 1.3 11/24/99

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